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    Author information
    First name: Jingwei
    Last name: Lu
    DBLP: 06/972
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    Below you find the publications which have been written by this author.

    Show item 1 to 17 of 17  
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    Conference paper
    Jingwei Lu, Hao Zhuang, Ilgweon Kang, Pengwen Chen, Chung-Kuan Cheng.
    ePlace-3D: Electrostatics based Placement for 3D-ICs.
    Proceedings of the 2016 on International Symposium on Physical Design, ISPD 2016, Santa Rosa, CA, USA, April 3-6, 2016 2016 (0) 2016
    Conference paper
    Jingwei Lu, Pengwen Chen, Chin-Chih Chang, Lu Sha, Dennis Jen-Hsin Huang, Chin-Chi Teng, Chung-Kuan Cheng.
    ePlace: Electrostatics-Based Placement Using Fast Fourier Transform and Nesterov's Method.
    ACM Trans. Design Autom. Electr. Syst. 2014, Volume 20 (0) 2015
    Conference paper
    Jingwei Lu, Hao Zhuang, Pengwen Chen, Hongliang Chang, Chin-Chih Chang, Yiu-Chung Wong, Lu Sha, Dennis J.-H. Huang, Yufeng Luo, Chin-Chi Teng, Chung-Kuan Cheng.
    ePlace-MS: Electrostatics-Based Placement for Mixed-Size Circuits.
    IEEE Trans. on CAD of Integrated Circuits and Systems 2015, Volume 34 (0) 2015
    Conference paper
    Hao Zhuang, Wenjian Yu, Shih-Hung Weng, Ilgweon Kang, Jeng-Hau Lin, Xiang Zhang, Ryan Coutts, Jingwei Lu, Chung-Kuan Cheng.
    Simulation Algorithms with Exponential Integration for Time-Domain Analysis of Large-Scale Power Delivery Networks.
    CoRR 2015, Volume 0 (0) 2015
    Conference paper
    Jingwei Lu, Hao Zhuang, Ilgweon Kang, Pengwen Chen, Chung-Kuan Cheng.
    ePlace-3D: Electrostatics based Placement for 3D-ICs.
    CoRR 2015, Volume 0 (0) 2015
    Conference paper
    Jingwei Lu, Pengwen Chen, Chin-Chih Chang, Lu Sha, Dennis J.-H. Huang, Chin-Chi Teng, Chung-Kuan Cheng.
    ePlace: Electrostatics Based Placement Using Nesterov's Method.
    The 51st Annual Design Automation Conference 2014, DAC '14, San Francisco, CA, USA, June 1-5, 2014 2014 (0) 2014
    Conference paper
    Xiang Zhang, Jingwei Lu, Yang Liu, Chung-Kuan Cheng.
    Worst-case noise area prediciton of on-chip power distribution network.
    ACM/IEEE International Workshop on System Level Interconnect Prediction, SLIP 2014, San Francisco, CA, USA, June 1, 2014 2014 (0) 2014
    Conference paper
    Qi Jing, Athanasios V. Vasilakos, Jiafu Wan, Jingwei Lu, Dechao Qiu.
    Security of the Internet of Things: perspectives and challenges.
    Wireless Networks 2014, Volume 20 (0) 2014
    Conference paper
    Jingwei Lu, Chiu-Wing Sham.
    LMgr: A low-M emory global router with dynamic topology update and bending-aware optimum path search.
    International Symposium on Quality Electronic Design, ISQED 2013, Santa Clara, CA, USA, March 4-6, 2013 2013 (0) 2013
    Conference paper
    Jingwei Lu, Pengwen Chen, Chin-Chih Chang, Lu Sha, Dennis Jen-Hsin Huang, Chin-Chi Teng, Chung-Kuan Cheng.
    FFTPL: An Analytic Placement Algorithm Using Fast Fourier Transform for Density Equalization.
    CoRR 2013, Volume 0 (0) 2013
    Conference paper
    Jingwei Lu, Pengwen Chen, Chin-Chih Chang, Lu Sha, Dennis Jen-Hsin Huang, Chin-Chi Teng, Chung-Kuan Cheng.
    FFTPL: An analytic placement algorithm using fast fourier transform for density equalization.
    IEEE 10th International Conference on ASIC, ASICON 2013, Shenzhen, China, October 28-31, 2013 2013 (0) 2013
    Conference paper
    Jingwei Lu, Wing-Kai Chow, Chiu-Wing Sham.
    A new clock network synthesizer for modern VLSI designs.
    Integration 2012, Volume 45 (0) 2012
    Conference paper
    Jingwei Lu, Wing-Kai Chow, Chiu-Wing Sham.
    Fast Power- and Slew-Aware Gated Clock Tree Synthesis.
    IEEE Trans. VLSI Syst. 2012, Volume 20 (0) 2012
    Conference paper
    Sung Kyu Han, Kwangok Jeong, Andrew B. Kahng, Jingwei Lu.
    Stability and scalability in global routing.
    2011 International Workshop on System Level Interconnect Prediction, SLIP 2011, San Diego, CA, USA, June 5, 2011 2011 (0) 2011
    Conference paper
    Jingwei Lu, Wing-Kai Chow, Chiu-Wing Sham, Evangeline F. Y. Young.
    A dual-MST approach for clock network synthesis.
    Proceedings of the 15th Asia South Pacific Design Automation Conference, ASP-DAC 2010, Taipei, Taiwan, January 18-21, 2010 2010 (0) 2010
    Conference paper
    Jingwei Lu, Wing-Kai Chow, Chiu-Wing Sham.
    Clock Network Synthesis with Concurrent Gate Insertion.
    Integrated Circuit and System Design. Power and Timing Modeling, Optimization, and Simulation - 20th International Workshop, PATMOS 2010, Grenoble, France, September 7-10, 2010, Revised Selected Papers 2011 (0) 2010
    Conference paper
    Chiu-Wing Sham, Evangeline F. Y. Young, Jingwei Lu.
    Congestion prediction in early stages of physical design.
    ACM Trans. Design Autom. Electr. Syst. 2009, Volume 14 (0) 2009
    Show item 1 to 17 of 17  

    Your query returned 17 matches in the database.