Publications
Search

Publications :: Search

Show author

On this page you see the details of the selected author.

    Author information
    First name: Sudhakar
    Last name: Yalamanchili
    DBLP: 14/5230
    Rating: (not rated yet)
    Bookmark:

    Below you find the publications which have been written by this author.

    Show item 1 to 10 of 155  
    Select a publication
    Show Title Venue Rating Date
    Conference paper
    Karthik Rao, Jun Wang, Sudhakar Yalamanchili, Yorai Wardi, Handong Ye.
    Application-Specific Performance-Aware Energy Optimization on Android Mobile Devices.
    2017 IEEE International Symposium on High Performance Computer Architecture, HPCA 2017, Austin, TX, USA, February 4-8, 2017 2017 (0) 2017
    Journal article
    Ramyad Hadidi, Bahar Asgari, Burhan Ahmad Mudassar, Saibal Mukhopadhyay, Sudhakar Yalamanchili, Hyesoon Kim.
    Demystifying the Characteristics of 3D-Stacked Memories: A Case Study for Hybrid Memory Cube.
    CoRR 2017, Volume 0 (0) 2017
    Conference paper
    Jun Wang, Zhenjiang Dong, Sudhakar Yalamanchili, George F. Riley.
    FNM: An Enhanced Null-Message Algorithm for Parallel Simulation of Multicore Systems.
    ACM Trans. Model. Comput. Simul. 2016, Volume 26 (0) 2016
    Conference paper
    Daniel Zinn, Haicheng Wu, Jin Wang, Molham Aref, Sudhakar Yalamanchili.
    General-purpose join algorithms for large graph triangle listing on heterogeneous systems.
    Proceedings of the 9th Annual Workshop on General Purpose Processing using Graphics Processing Unit, GPGPU@PPoPP 2016, Barcelona, Spain, March 12 - 16, 2016 2016 (0) 2016
    Conference paper
    William J. Song, Saibal Mukhopadhyay, Sudhakar Yalamanchili.
    Amdahl's law for lifetime reliability scaling in heterogeneous multicore processors.
    2016 IEEE International Symposium on High Performance Computer Architecture, HPCA 2016, Barcelona, Spain, March 12-16, 2016 2016 (0) 2016
    Conference paper
    Xinwei Chen, Yorai Wardi, Sudhakar Yalamanchili.
    IPA in the Loop: Control Design for Throughput Regulation in Computer Processors.
    CoRR 2016, Volume 0 (0) 2016
    Conference paper
    X. Chen, Yorai Wardi, Sudhakar Yalamanchili.
    IPA in the loop: Control design for throughput regulation in computer processors.
    13th International Workshop on Discrete Event Systems, WODES 2016, Xi'an, China, May 30 - June 1, 2016 2016 (0) 2016
    Conference paper
    Jin Wang, Norman Rubin, Albert Sidelnik, Sudhakar Yalamanchili.
    LaPerm: Locality Aware Scheduler for Dynamic Parallelism on GPUs.
    43rd ACM/IEEE Annual International Symposium on Computer Architecture, ISCA 2016, Seoul, South Korea, June 18-22, 2016 2016 (0) 2016
    Conference paper
    Duckhwan Kim 0001, Jaeha Kung, Sek M. Chai, Sudhakar Yalamanchili, Saibal Mukhopadhyay.
    Neurocube: A Programmable Digital Neuromorphic Architecture with High-Density 3D Memory.
    43rd ACM/IEEE Annual International Symposium on Computer Architecture, ISCA 2016, Seoul, South Korea, June 18-22, 2016 2016 (0) 2016
    Conference paper
    Syed Minhaj Hassan, Sudhakar Yalamanchili.
    Understanding the Impact of Air and Microfluidics Cooling on Performance of 3D Stacked Memory Systems.
    Proceedings of the Second International Symposium on Memory Systems, MEMSYS 2016, Alexandria, VA, USA, October 3-6, 2016 2016 (0) 2016
    Show item 1 to 10 of 155  

    Your query returned 155 matches in the database.