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    Author information
    First name: Rainer
    Last name: Leupers
    DBLP: 14/6306
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    Below you find the publications which have been written by this author.

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    Conference paper
    Jan Weinstock, Rainer Leupers, Gerd Ascheid.
    Accelerating MPSoC Simulation Using Parallel SystemC and Processor Sleep Models.
    Proceedings of the 9th Workshop on Rapid Simulation and Performance Evaluation: Methods and Tools, RAPIDO 2017, Stockholm, Sweden, January 23-25, 2017 2017 (0) 2017
    Conference paper
    María H. Auras-Rodríguez, Anthony Zimmermann, Gerd Ascheid, Rainer Leupers.
    Using PEGs for Automatic Extraction of Memory Access Descriptions to Support Data-Parallel Pattern Recognition.
    Proceedings of the 8th Workshop and 6th Workshop on Parallel Programming and Run-Time Management Techniques for Many-core Architectures and Design Tools and Architectures for Multicore Embedded Computing Platforms, PARMA-DITAM@HiPEAC 2017, Stockholm, Swed 2017 (0) 2017
    Conference paper
    Miguel Angel Aguilar, Rainer Leupers, Gerd Ascheid, Nikolaos Kavvadias, Liam Fitzpatrick.
    Schedule-aware loop parallelization for embedded MPSoCs by exploiting parallel slack.
    Design, Automation Test in Europe Conference Exhibition, DATE 2017, Lausanne, Switzerland, March 27-31, 2017 2017 (0) 2017
    Conference paper
    Miguel Angel Aguilar, Juan Fernando Eusse Giraldo, Projjol Ray, Rainer Leupers, Gerd Ascheid, Weihua Sheng, Prashant Sharma.
    Towards Parallelism Extraction for Heterogeneous Multicore Android Devices.
    International Journal of Parallel Programming 2017, Volume 45 (0) 2017
    Conference paper
    Andreas Bytyn, Jannik Springer, Rainer Leupers, Gerd Ascheid.
    VLSI implementation of LS-SVM training and classification using entropy based subset-selection.
    IEEE International Symposium on Circuits and Systems, ISCAS 2017, Baltimore, MD, USA, May 28-31, 2017 2017 (0) 2017
    Conference paper
    Miguel Angel Aguilar, Abhishek Aggarwal, Awaid Shaheen, Rainer Leupers, Gerd Ascheid, Jerónimo Castrillón, Liam Fitzpatrick.
    Multi-grained performance estimation for MPSoC compilers: work-in-progress.
    Proceedings of the 2017 International Conference on Compilers, Architectures and Synthesis for Embedded Systems, CASES 2017, Seoul, Republic of Korea, October 15-20, 2017 2017 (0) 2017
    Conference paper
    Daniel Günther, Rainer Leupers, Gerd Ascheid.
    Efficiency Enablers of Lightweight SDR for MIMO Baseband Processing.
    IEEE Trans. VLSI Syst. 2016, Volume 24 (0) 2016
    Conference paper
    Marius Marcu, Oana Boncalo, Madalin Ghenea, Alexandru Amaricai, Jan Weinstock, Rainer Leupers, Zheng Wang 0027, Giorgis Georgakoudis, Dimitrios S. Nikolopoulos, Cosmin Cernazanu-Glavan, Lucian Bara, Marian Ionascu.
    Low-Cost Hardware Infrastructure for Runtime Thread Level Energy Accounting.
    Architecture of Computing Systems - ARCS 2016 - 29th International Conference, Nuremberg, Germany, April 4-7, 2016, Proceedings 2016 (0) 2016
    Conference paper
    Gereon Onnebrink, Stefan Schürmans, Florian Walbroel, Rainer Leupers, Gerd Ascheid, Xiaotao Chen, YwhPyng Harn.
    Black box power estimation for digital signal processors using virtual platforms.
    Proceedings of the 2016 Workshop on Rapid Simulation and Performance Evaluation - Methods and Tools, RAPIDO@HiPEAC 2016, Prague, Czech Republic, January 18, 2016 2016 (0) 2016
    Conference paper
    Daniel Günther, Tomas Henriksson, Rainer Leupers, Gerd Ascheid.
    Mantissa-masking for energy-efficient floating-point LTE uplink MIMO baseband processing.
    2016 Design, Automation Test in Europe Conference Exhibition, DATE 2016, Dresden, Germany, March 14-18, 2016 2016 (0) 2016
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