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First name:	Yuh-Fang
Last name:	Tsai
DBLP:	14/6549
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	Conference paper Yuh-Fang Tsai, Feng Wang 0004, Yuan Xie, Narayanan Vijaykrishnan, Mary Jane Irwin. Design Space Exploration for 3-D Cache.	IEEE Trans. VLSI Syst. 2008, Volume 16	(0)	2008
	Conference paper Yuh-Fang Tsai, Narayanan Vijaykrishnan, Yuan Xie, Mary Jane Irwin. Leakage-Aware Interconnect for On-Chip Network	CoRR 2007, Volume 0	(0)	2007
	Conference paper Wei Zhang 0002, Yuh-Fang Tsai, David Duarte, Narayanan Vijaykrishnan, Mahmut T. Kandemir, Mary Jane Irwin. Reducing dynamic and leakage energy in VLIW architectures.	ACM Trans. Embedded Comput. Syst. 2006, Volume 5	(0)	2006
	Conference paper Yuh-Fang Tsai, Narayanan Vijaykrishnan, Yuan Xie, Mary Jane Irwin. Leakage-Aware Interconnect for On-Chip Network.	2005 Design, Automation and Test in Europe Conference and Exposition (DATE 2005), 7-11 March 2005, Munich, Germany 2005	(0)	2005
	Conference paper Yuh-Fang Tsai, Yuan Xie, Narayanan Vijaykrishnan, Mary Jane Irwin. Three-Dimensional Cache Design Exploration Using 3DCacti.	23rd International Conference on Computer Design (ICCD 2005), 2-5 October 2005, San Jose, CA, USA 2005	(0)	2005
	Conference paper Yuh-Fang Tsai, Narayanan Vijaykrishnan, Yuan Xie, Mary Jane Irwin. Influence of Leakage Reduction Techniques on Delay/Leakage Uncertainty.	18th International Conference on VLSI Design (VLSI Design 2005), with the 4th International Conference on Embedded Systems Design, 3-7 January 2005, Kolkata, India 2005	(0)	2005
	Conference paper Yuh-Fang Tsai, Ananth Hegde, Narayanan Vijaykrishnan, Mary Jane Irwin, Theocharis Theocharides. ChipPower: an architecture-level leakage simulator.	Proceedings 2004 IEEE International SOC Conference, September 12-15, 2004, Hilton Santa Clara, CA, USA 2004	(0)	2004
	Conference paper Aman Gayasen, Yuh-Fang Tsai, Narayanan Vijaykrishnan, Mahmut T. Kandemir, Mary Jane Irwin, Tim Tuan. Reducing leakage energy in FPGAs using region-constrained placement.	Proceedings of the ACM/SIGDA 12th International Symposium on Field Programmable Gate Arrays, FPGA 2004, Monterey, California, USA, February 22-24, 2004 2004	(0)	2004
	Conference paper Yuh-Fang Tsai, D. E. Duarte, Narayanan Vijaykrishnan, Mary Jane Irwin. Characterization and modeling of run-time techniques for leakage power reduction.	IEEE Trans. VLSI Syst. 2004, Volume 12	(0)	2004
	Conference paper Yuh-Fang Tsai, David Duarte, Narayanan Vijaykrishnan, Mary Jane Irwin. Implications of technology scaling on leakage reduction techniques.	Proceedings of the 40th Design Automation Conference, DAC 2003, Anaheim, CA, USA, June 2-6, 2003 2003	(0)	2003
	Conference paper Lin Li, Ismail Kadayif, Yuh-Fang Tsai, Narayanan Vijaykrishnan, Mahmut T. Kandemir, Mary Jane Irwin, Anand Sivasubramaniam. Managing Leakage Energy in Cache Hierarchies.	J. Instruction-Level Parallelism 2003, Volume 5	(0)	2003
	Conference paper Lin Li, Ismail Kadayif, Yuh-Fang Tsai, Narayanan Vijaykrishnan, Mahmut T. Kandemir, Mary Jane Irwin, Anand Sivasubramaniam. Leakage Energy Management in Cache Hierarchies.	2002 International Conference on Parallel Architectures and Compilation Techniques (PACT 2002), 22-25 September 2002, Charlottesville, VA, USA 2002	(0)	2002
	Conference paper David Duarte, Yuh-Fang Tsai, Narayanan Vijaykrishnan, Mary Jane Irwin. Evaluating Run-Time Techniques for Leakage Power Reduction.	Proceedings of the ASPDAC 2002 / VLSI Design 2002, CD-ROM, 7-11 January 2002, Bangalore, India 2002	(0)	2002
	Conference paper Wei Zhang 0002, Narayanan Vijaykrishnan, Mahmut T. Kandemir, Mary Jane Irwin, David Duarte, Yuh-Fang Tsai. Exploiting VLIW schedule slacks for dynamic and leakage energy reduction.	Proceedings of the 34th Annual International Symposium on Microarchitecture, Austin, Texas, USA, December 1-5, 2001 2001	(0)	2001

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