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First name:	Yu-Shih
Last name:	Su
DBLP:	27/6936
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	Conference paper Pei-Wen Luo, Chun Zhang, Yung-Tai Chang, Liang-Chia Cheng, Hung-Hsie Lee, Bih-Lan Sheu, Yu-Shih Su, Ding-Ming Kwai, Yiyu Shi. Benchmarking for research in power delivery networks of three-dimensional integrated circuits.	International Symposium on Physical Design, ISPD'13, Stateline, NV, USA, March 24-27, 2013 2013	(0)	2013
	Conference paper Tao Wang, Pei-Wen Luo, Yu-Shih Su, Liang-Chia Cheng, Ding-Ming Kwai, Yiyu Shi. Capturing the phantom of the power grid - on the runtime adaptive techniques for noise reduction.	Proceedings of the 17th Asia and South Pacific Design Automation Conference, ASP-DAC 2012, Sydney, Australia, January 30 - February 2, 2012 2012	(0)	2012
	Conference paper Yu-Shih Su, Da-Chung Wang, Shih-Chieh Chang, Malgorzata Marek-Sadowska. Performance Optimization Using Variable-Latency Design Style.	IEEE Trans. VLSI Syst. 2011, Volume 19	(0)	2011
	Conference paper Chiao-Ling Lung, Yu-Shih Su, Shih-Hsiu Huang, Yiyu Shi, Shih-Chieh Chang. Fault-tolerant 3D clock network.	Proceedings of the 48th Design Automation Conference, DAC 2011, San Diego, California, USA, June 5-10, 2011 2011	(0)	2011
	Conference paper Yu-Shih Su, Wing-Kai Hon, Cheng-Chih Yang, Shih-Chieh Chang, Yeong-Jar Chang. Clock Skew Minimization in Multi-Voltage Mode Designs Using Adjustable Delay Buffers.	IEEE Trans. on CAD of Integrated Circuits and Systems 2010, Volume 29	(0)	2010
	Conference paper Yu-Shih Su, Wing-Kai Hon, Cheng-Chih Yang, Shih-Chieh Chang, Yeong-Jar Chang. Value assignment of adjustable delay buffers for clock skew minimization in multi-voltage mode designs.	2009 International Conference on Computer-Aided Design (ICCAD'09), November 2-5, 2009, San Jose, CA, USA 2009	(0)	2009
	Conference paper Yu-Shih Su, Po-Hsien Chang, Shih-Chieh Chang, TingTing Hwang. Synthesis of a novel timing-error detection architecture.	ACM Trans. Design Autom. Electr. Syst. 2008, Volume 13	(0)	2008
	Conference paper Yu-Shih Su, Da-Chung Wang, Shih-Chieh Chang, Malgorzata Marek-Sadowska. An Efficient Mechanism for Performance Optimization of Variable-Latency Designs.	Proceedings of the 44th Design Automation Conference, DAC 2007, San Diego, CA, USA, June 4-8, 2007 2007	(0)	2007

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