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First name:	Peter M. W.
Last name:	Knijnenburg
DBLP:	36/410
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	Conference paper Sven van Haastregt, Peter M. W. Knijnenburg. Interactive presentation: Feasibility of combined area and performance optimization for superscalar processors using random search.	2007 Design, Automation and Test in Europe Conference and Exposition (DATE 2007), April 16-20, 2007, Nice, France 2007	(0)	2007
	Conference paper Francisco J. Cazorla, Enrique Fernández, Peter M. W. Knijnenburg, Alex Ramírez, Rizos Sakellariou, Mateo Valero. On the Problem of Minimizing Workload Execution Time in SMT Processors.	Proceedings of the 2007 International Conference on Embedded Computer Systems: Architectures, Modeling and Simulation (IC-SAMOS 2007), Samos, Greece, July 16-19, 2007 2007	(0)	2007
	Conference paper Thomas A. M. Bernard, Chris R. Jesshope, Peter M. W. Knijnenburg. Strategies for Compiling µ TC to Novel Chip Multiprocessors.	Embedded Computer Systems: Architectures, Modeling, and Simulation, 7th International Workshop, SAMOS 2007, Samos, Greece, July 16-19, 2007, Proceedings 2007	(0)	2007
	Conference paper Masayo Haneda, Peter M. W. Knijnenburg, Harry A. G. Wijshoff. On the impact of data input sets on statistical compiler tuning.	20th International Parallel and Distributed Processing Symposium (IPDPS 2006), Proceedings, 25-29 April 2006, Rhodes Island, Greece 2006	(0)	2006
	Conference paper Masayo Haneda, Peter M. W. Knijnenburg, Harry A. G. Wijshoff. Code Size Reduction by Compiler Tuning.	Embedded Computer Systems: Architectures, Modeling, and Simulation, 6th International Workshop, SAMOS 2006, Samos, Greece, July 17-20, 2006, Proceedings 2006	(0)	2006
	Conference paper Karine Heydemann, François Bodin, Peter M. W. Knijnenburg, Laurent Morin. UFS: a global trade-off strategy for loop unrolling for VLIW architectures.	Concurrency and Computation: Practice and Experience 2006, Volume 18	(0)	2006
	Conference paper Peter M. W. Knijnenburg. Special Issue: 10th International Workshop on Compilers for Parallel Computers (CPC 2003).	Concurrency and Computation: Practice and Experience 2006, Volume 18	(0)	2006
	Conference paper Francisco J. Cazorla, Peter M. W. Knijnenburg, Rizos Sakellariou, Enrique Fernández, Alex Ramírez, Mateo Valero. Predictable Performance in SMT Processors: Synergy between the OS and SMTs.	IEEE Trans. Computers 2006, Volume 55	(0)	2006
	Conference paper Masayo Haneda, Peter M. W. Knijnenburg, Harry A. G. Wijshoff. Automatic Selection of Compiler Options Using Non-parametric Inferential Statistics.	14th International Conference on Parallel Architecture and Compilation Techniques (PACT 2005), 17-21 September 2005, St. Louis, MO, USA 2005	(0)	2005
	Conference paper Francisco J. Cazorla, Peter M. W. Knijnenburg, Rizos Sakellariou, Enrique Fernández, Alex Ramírez, Mateo Valero. Architectural support for real-time task scheduling in SMT processors.	Proceedings of the 2005 International Conference on Compilers, Architecture, and Synthesis for Embedded Systems, CASES 2005, San Francisco, California, USA, September 24-27, 2005 2005	(0)	2005
	Conference paper Masayo Haneda, Peter M. W. Knijnenburg, Harry A. G. Wijshoff. Optimizing general purpose compiler optimization.	Proceedings of the Second Conference on Computing Frontiers, 2005, Ischia, Italy, May 4-6, 2005 2005	(0)	2005
	Conference paper Masayo Haneda, Peter M. W. Knijnenburg, Harry A. G. Wijshoff. Generating new general compiler optimization settings.	Proceedings of the 19th Annual International Conference on Supercomputing, ICS 2005, Cambridge, Massachusetts, USA, June 20-22, 2005 2005	(0)	2005
	Conference paper Francisco J. Cazorla, Peter M. W. Knijnenburg, Rizos Sakellariou, Enrique Fernández, Alex Ramírez, Mateo Valero. Predictable performance in SMT processors.	Proceedings of the First Conference on Computing Frontiers, 2004, Ischia, Italy, April 14-16, 2004 2004	(0)	2004
	Conference paper Francisco J. Cazorla, Peter M. W. Knijnenburg, Rizos Sakellariou, Enrique Fernández, Alex Ramírez, Mateo Valero. Implicit vs. Explicit Resource Allocation in SMT Processors.	2004 Euromicro Symposium on Digital Systems Design (DSD 2004), Architectures, Methods and Tools, 31 August - 3 September 2004, Rennes, France 2004	(0)	2004
	Conference paper Francisco J. Cazorla, Peter M. W. Knijnenburg, Rizos Sakellariou, Enrique Fernández, Alex Ramírez, Mateo Valero. Feasibility of QoS for SMT.	Euro-Par 2004 Parallel Processing, 10th International Euro-Par Conference, Pisa, Italy, August 31-September 3, 2004, Proceedings 2004	(0)	2004
	Conference paper Rogier P. J. Pinkers, Peter M. W. Knijnenburg, Masayo Haneda, Harry A. G. Wijshoff. Statistical Selection of Compiler Options.	12th International Workshop on Modeling, Analysis, and Simulation of Computer and Telecommunication Systems (MASCOTS 2004), 4-8 October 2004, Vollendam, The Netherlands 2004	(0)	2004
	Conference paper Peter M. W. Knijnenburg, Toru Kisuki, Kyle A. Gallivan, Michael F. P. O'Boyle. The effect of cache models on iterative compilation for combined tiling and unrolling.	Concurrency - Practice and Experience 2004, Volume 16	(0)	2004
	Conference paper Francisco J. Cazorla, Alex Ramírez, Mateo Valero, Peter M. W. Knijnenburg, Rizos Sakellariou, Enrique Fernández. QoS for High-Performance SMT Processors in Embedded Systems.	IEEE Micro 2004, Volume 24	(0)	2004
	Conference paper Peter M. W. Knijnenburg, Toru Kisuki, Michael F. P. O'Boyle. Combined Selection of Tile Sizes and Unroll Factors Using Iterative Compilation.	The Journal of Supercomputing 2003, Volume 24	(0)	2003
	Conference paper Grigori Fursin, Michael F. P. O'Boyle, Peter M. W. Knijnenburg. Evaluating Iterative Compilation.	Languages and Compilers for Parallel Computing, 15th Workshop, LCPC 2002, College Park, MD, USA, July 25-27, 2002, Revised Papers 2005	(0)	2002
	Conference paper Peter M. W. Knijnenburg, Toru Kisuki, Michael F. P. O'Boyle. Iterative Compilation.	Embedded Processor Design Challenges: Systems, Architectures, Modeling, and Simulation - SAMOS 2002	(0)	2002
	Conference paper Michael F. P. O'Boyle, Peter M. W. Knijnenburg. Integrating Loop and Data Transformations for Global Optimization.	J. Parallel Distrib. Comput. 2002, Volume 62	(0)	2002
	Conference paper Peter M. W. Knijnenburg, Toru Kisuki, Kyle A. Gallivan. Cache Models for Iterative Compilation.	Euro-Par 2001: Parallel Processing, 7th International Euro-Par Conference Manchester, UK August 28-31, 2001, Proceedings 2001	(0)	2001
	Conference paper Toru Kisuki, Peter M. W. Knijnenburg, Michael F. P. O'Boyle. Combined Selection of Tile Sizes and Unroll Factors Using Iterative Compilation.	IEEE PACT 2000	(0)	2000
	Conference paper Henri E. Bal, Raoul Bhoedjang, Rutger F. H. Hofman, Ceriel J. H. Jacobs, Thilo Kielmann, Jason Maassen, Rob van Nieuwpoort, John Romain, Luc Renambot, Tim Rühl, Ronald Veldema, Kees Verstoep, Aline Baggio, Gerco Ballintijn, Ihor Kuz, Guillaume Pierre, Maarten van Steen, Andrew S. Tanenbaum, Gerben Doornbos, Desmond Germans, Hans J. W. Spoelder, Evert Jan Baerends, Stan J. A. van Gisbergen, Hamid Afsermanseh, G. Dick van Albada, Adam Belloum, David Dubbeldam, Zeger W. Hendrikse, Louis O. Hertzberger, Alfons G. Hoekstra, Kamil Iskra, Drona Kandhai, Dennis Koelma, Frank van der Linden, Benno J. Overeinder, Peter M. A. Sloot, Piero Spinnato, Dick H. J. Epema, Arjan J. C. van Gemund, Pieter P. Jonker, Andrei Radulescu, Kees van Reeuwijk, Henk J. Sips, Peter M. W. Knijnenburg, Michael S. Lew, Floris Sluiter, Lex Wolters, Hans Blom, Cees T. A. M. de Laat. The Distributed ASCI Supercomputer Project.	Operating Systems Review 2000, Volume 34	(0)	2000

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