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First name:	Elisardo
Last name:	Antelo
DBLP:	48/2572
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	Conference paper Lois Orosa, Elisardo Antelo, Javier D. Bruguera. FlexSig: Implementing flexible hardware signatures.	TACO 2011, Volume 8	(0)	2012
	Conference paper Elisardo Antelo, David Hough, Paolo Ienne. Guest Editors' Introduction: Special Section on Computer Arithmetic.	IEEE Trans. Computers 2012, Volume 61	(0)	2012
	Conference paper Álvaro Vázquez, Julio Villalba, Elisardo Antelo, Emilio L. Zapata. Redundant Floating-Point Decimal CORDIC Algorithm.	IEEE Trans. Computers 2012, Volume 61	(0)	2012
	Conference paper Fabrizio Lamberti, Nikolaos Andrikos, Elisardo Antelo, Paolo Montuschi. Reducing the Computation Time in (Short Bit-Width) Two's Complement Multipliers.	IEEE Trans. Computers 2011, Volume 60	(0)	2011
	Journal article Álvaro Vázquez, Elisardo Antelo, Paolo Montuschi. Improved Design of High-Performance Parallel Decimal Multipliers.	IEEE Trans. Computers 2010, Volume 59	(0)	2010
	Journal article Elisardo Antelo. A Comment on "Beyond Fat-tree: Unidirectional Load-Balanced Multistage Interconnection Network".	Computer Architecture Letters 2009, Volume 8	(0)	2009
	Conference paper Álvaro Vázquez, Elisardo Antelo. A High-Performance Significand BCD Adder with IEEE 754-2008 Decimal Rounding.	19th IEEE Symposium on Computer Arithmetic, ARITH 2009, Portland, Oregon, USA, 9-10 June 2009 2009	(0)	2009
	Conference paper Álvaro Vázquez, Julio Villalba, Elisardo Antelo. Computation of Decimal Transcendental Functions Using the CORDIC Algorithm.	19th IEEE Symposium on Computer Arithmetic, ARITH 2009, Portland, Oregon, USA, 9-10 June 2009 2009	(0)	2009
	Conference paper Álvaro Vázquez, Elisardo Antelo. New insights on Ling adders.	19th IEEE International Conference on Application-Specific Systems, Architectures and Processors, ASAP 2008, July 2-4, 2008, Leuven, Belgium 2008	(0)	2008
	Conference paper Elisardo Antelo, Julio Villalba, Emilio L. Zapata. A Low-Latency Pipelined 2D and 3D CORDIC Processors.	IEEE Trans. Computers 2008, Volume 57	(0)	2008

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