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    Author information
    First name: Norbert
    Last name: Wehn
    DBLP: 48/6980
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    Below you find the publications which have been written by this author.

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    Conference paper
    Deepak M. Mathew, Éder Zulian, Subash Kannoth, Matthias Jung 0001, Christian Weis, Norbert Wehn.
    A Bank-Wise DRAM Power Model for System Simulations.
    Proceedings of the 9th Workshop on Rapid Simulation and Performance Evaluation: Methods and Tools, RAPIDO 2017, Stockholm, Sweden, January 23-25, 2017 2017 (0) 2017
    Conference paper
    Pei Liu, Ahmed Hemani, Kolin Paul, Christian Weis, Matthias Jung 0001, Norbert Wehn.
    A Customized Many-Core Hardware Acceleration Platform for Short Read Mapping Problems Using Distributed Memory Interface with 3D-Stacked Architecture.
    Signal Processing Systems 2017, Volume 87 (0) 2017
    Conference paper
    Vladimir Rybalkin, Norbert Wehn, Mohammad Reza Yousefi, Didier Stricker.
    Hardware architecture of Bidirectional Long Short-Term Memory Neural Network for Optical Character Recognition.
    Design, Automation Test in Europe Conference Exhibition, DATE 2017, Lausanne, Switzerland, March 27-31, 2017 2017 (0) 2017
    Conference paper
    Menbere Tekleyohannes, MohammadSadegh Sadri, Christian Weis, Norbert Wehn, Martin Klein 0005, Michael Siegrist.
    An advanced embedded architecture for connected component analysis in industrial applications.
    Design, Automation Test in Europe Conference Exhibition, DATE 2017, Lausanne, Switzerland, March 27-31, 2017 2017 (0) 2017
    Conference paper
    Stefan Weithoffer, Norbert Wehn.
    Enhanced decoding for high-rate LTE Turbo-Codes with short block lengths.
    2017 IEEE International Conference on Communications Workshops, ICC Workshops 2017, Paris, France, May 21-25, 2017 2017 (0) 2017
    Conference paper
    Javier Alejandro Varela, Norbert Wehn, Qian Liang, Songyin Tang.
    Exploiting Decoupled OpenCL Work-Items with Data Dependencies on FPGAs: A Case Study.
    2017 IEEE International Parallel and Distributed Processing Symposium Workshops, IPDPS Workshops 2017, Orlando / Buena Vista, FL, USA, May 29 - June 2, 2017 2017 (0) 2017
    Conference paper
    Sebastian Haas, Tobias Seifert, Benedikt Noethen, Stefan Scholze, Sebastian Höppner, Andreas Dixius, Esther P. Adeva, Thomas R. Augustin, Friedrich Pauls, Sadia Moriam, Mattis Hasler, Erik Fischer, Yong Chen, Emil Matús, Georg Ellguth, Stephan Hartmann, Stefan Schiefer, Love Cederstroem, Dennis Walter, Stephan Henker, Stefan Hänzsche, Johannes Uhlig, Holger Eisenreich, Stefan Weithoffer, Norbert Wehn, René Schüffny, Christian Mayr, Gerhard P. Fettweis.
    A Heterogeneous SDR MPSoC in 28 nm CMOS for Low-Latency Wireless Applications.
    Proceedings of the 54th Annual Design Automation Conference, DAC 2017, Austin, TX, USA, June 18-22, 2017 2017 (0) 2017
    Conference paper
    Matthias Jung 0001, Deepak M. Mathew, Carl Christian Rheinländer, Christian Weis, Norbert Wehn.
    A Platform to Analyze DDR3 DRAM's Power and Retention Time.
    IEEE Design Test 2017, Volume 34 (0) 2017
    Conference paper
    Pei Liu, Ahmed Hemani, Kolin Paul, Christian Weis, Matthias Jung 0001, Norbert Wehn.
    3D-Stacked Many-Core Architecture for Biological Sequence Analysis Problems.
    International Journal of Parallel Programming 2017, Volume 45 (0) 2017
    Conference paper
    Christian Weis, Abdul Mutaal, Omar Naji, Matthias Jung 0001, Andreas Hansson, Norbert Wehn.
    DRAMSpec: A High-Level DRAM Timing, Power and Area Exploration Tool.
    International Journal of Parallel Programming 2017, Volume 45 (0) 2017
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