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First name:	Bingfeng
Last name:	Mei
DBLP:	78/3930
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	Journal article Bjorn De Sutter, Osman Allam, Praveen Raghavan, Roeland Vandebriel, Hans Cappelle, Tom Vander Aa, Bingfeng Mei. An Efficient Memory Organization for High-ILP Inner Modem Baseband SDR Processors.	Signal Processing Systems 2010, Volume 61	(0)	2010
	Journal article Andy Lambrechts, Praveen Raghavan, Murali Jayapala, Bingfeng Mei, Francky Catthoor, Diederik Verkest. Interconnect Exploration for Energy Versus Performance Tradeoffs for Coarse Grained Reconfigurable Architectures.	IEEE Trans. VLSI Syst. 2009, Volume 17	(0)	2009
	Conference paper Mladen Berekovic, Andreas Kanstein, Bingfeng Mei, Bjorn De Sutter. Mapping of nomadic multimedia applications on the ADRES reconfigurable array processor.	Microprocessors and Microsystems - Embedded Hardware Design 2009, Volume 33	(0)	2009
	Conference paper Bjorn De Sutter, Paul Coene, Tom Vander Aa, Bingfeng Mei. Placement-and-routing-based register allocation for coarse-grained reconfigurable arrays.	Proceedings of the 2008 ACM SIGPLAN/SIGBED Conference on Languages, Compilers, and Tools for Embedded Systems (LCTES'08), Tucson, AZ, USA, June 12-13, 2008 2008	(0)	2008
	Conference paper Bingfeng Mei, Bjorn De Sutter, Tom Vander Aa, M. Wouters, Andreas Kanstein, Steven Dupont. Implementation of a Coarse-Grained Reconfigurable Media Processor for AVC Decoder.	Signal Processing Systems 2008, Volume 51	(0)	2008
	Conference paper Tom Vander Aa, Bingfeng Mei, Bjorn De Sutter. A backtracking instruction scheduler using predicate-based code hoisting to fill delay slots.	Proceedings of the 2007 International Conference on Compilers, Architecture, and Synthesis for Embedded Systems, CASES 2007, Salzburg, Austria, September 30 - October 3, 2007 2007	(0)	2007
	Conference paper Bjorn De Sutter, Bingfeng Mei, Andrei Bartic, Tom Vander Aa, Mladen Berekovic, Jean-Yves Mignolet, Kris Croes, Paul Coene, Miro Cupac, Aïssa Couvreur, Andy Folens, Steven Dupont, Bert Van Thielen, Andreas Kanstein, Hong-Seok Kim, Suk Jin Kim. Hardware and a Tool Chain for ADRES.	Reconfigurable Computing: Architectures and Applications, Second International Workshop, ARC 2006, Delft, The Netherlands, March 1-3, 2006, Revised Selected Papers 2006	(0)	2006
	Conference paper Bingfeng Mei, Francisco-Javier Veredas, Bart Masschelein. Mapping an H.264/AVC Decoder onto the ADRES Reconfigurable Architecture.	Proceedings of the 2005 International Conference on Field Programmable Logic and Applications (FPL), Tampere, Finland, August 24-26, 2005 2005	(0)	2005
	Conference paper Francisco-Javier Veredas, Michael Scheppler, Will Moffat, Bingfeng Mei. Custom Implementation of the Coarse-Grained Reconfigurable ADRES Architecture for Multimedia Purposes.	Proceedings of the 2005 International Conference on Field Programmable Logic and Applications (FPL), Tampere, Finland, August 24-26, 2005 2005	(0)	2005
	Conference paper Bingfeng Mei, Andy Lambrechts, Diederik Verkest, Jean-Yves Mignolet, Rudy Lauwereins. Architecture Exploration for a Reconfigurable Architecture Template.	IEEE Design Test of Computers 2005, Volume 22	(0)	2005
	Conference paper Steven J. E. Wilton, Noha Kafafi, Bingfeng Mei, Serge Vernalde. Interconnect architectures for modulo-scheduled coarse-grained reconfigurable arrays.	Proceedings of the 2004 IEEE International Conference on Field-Programmable Technology, Brisbane, Australia, December 6-8, 2004 2004	(0)	2004
	Conference paper Bingfeng Mei, Serge Vernalde, Diederik Verkest, Rudy Lauwereins. Design Methodology for a Tightly Coupled VLIW/Reconfigurable Matrix Architecture: A Case Study.	2004 Design, Automation and Test in Europe Conference and Exposition (DATE 2004), 16-20 February 2004, Paris, France 2004	(0)	2004
	Conference paper Andy Lambrechts, Tom Vander Aa, Murali Jayapala, Guillermo Talavera, Anthony Leroy, Adelina Shickova, Francisco Barat, Bingfeng Mei, Francky Catthoor, Diederik Verkest, Geert Deconinck, Henk Corporaal, Frédéric Robert, Jordi Carrabina. Design Style Case Study for Embedded Multi Media Compute Nodes.	Proceedings of the 25th IEEE Real-Time Systems Symposium (RTSS 2004), 5-8 December 2004, Lisbon, Portugal 2004	(0)	2004
	Conference paper Bingfeng Mei, Serge Vernalde, Diederik Verkest, Hugo De Man, Rudy Lauwereins. Exploiting Loop-Level Parallelism on Coarse-Grained Reconfigurable Architectures Using Modulo Scheduling.	2003 Design, Automation and Test in Europe Conference and Exposition (DATE 2003), 3-7 March 2003, Munich, Germany 2003	(0)	2003
	Conference paper Bingfeng Mei, Serge Vernalde, Diederik Verkest, Hugo De Man, Rudy Lauwereins. ADRES: An Architecture with Tightly Coupled VLIW Processor and Coarse-Grained Reconfigurable Matrix.	Field Programmable Logic and Application, 13th International Conference, FPL 2003, Lisbon, Portugal, September 1-3, 2003, Proceedings 2003	(0)	2003
	Conference paper Bingfeng Mei, Serge Vernalde, Diederik Verkest, Hugo De Man, Rudy Lauwereins. DRESC: a retargetable compiler for coarse-grained reconfigurable architectures.	Proceedings of the 2002 IEEE International Conference on Field-Programmable Technology, FPT 2002, Hong Kong, China, December 16-18, 2002 2002	(0)	2002
	Conference paper Yajun Ha, Bingfeng Mei, Patrick Schaumont, Serge Vernalde, Rudy Lauwereins, Hugo De Man. Development of a Design Framework for Platform-Independent Networked Reconfiguration of Software and Hardware.	Field-Programmable Logic and Applications, 11th International Conference, FPL 2001, Belfast, Northern Ireland, UK, August 27-29, 2001, Proceedings 2001	(0)	2001

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