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    Author information
    First name: Eugenio
    Last name: Villar
    DBLP: 78/5682
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    Conference paper
    Kim Grüttner, Ralph Görgen, Sören Schreiner, Fernando Herrera, Pablo Peñil, Julio L. Medina, Eugenio Villar, Gianluca Palermo, William Fornaciari, Carlo Brandolese, Davide Gadioli, Emanuele Vitali, Davide Zoni, Sara Bocchio, Luca Ceva, Paolo Azzoni, Massimo Poncino, Sara Vinco, Enrico Macii, Salvatore Cusenza, John M. Favaro, Raúl Valencia, Ingo Sander, Kathrin Rosvall, Nima Khalilzad, Davide Quaglia.
    CONTREX: Design of embedded mixed-criticality CONTRol systems under consideration of EXtra-functional properties.
    Microprocessors and Microsystems - Embedded Hardware Design 2017, Volume 51 (0) 2017
    Journal article
    Houcine Hassan, Laurence T. Yang, Chun Jason Xue, Eugenio Villar.
    Special issue on: "Heterogeneous architectures for Cyber-physical systems (HACPS)".
    Microprocessors and Microsystems - Embedded Hardware Design 2017, Volume 52 (0) 2017
    Conference paper
    Héctor Posadas, Luis Diaz, Eugenio Villar.
    Static Write Buffer Cache Modeling to Increase Host-Compiled Simulation Accuracy.
    Euromicro Conference on Digital System Design, DSD 2017, Vienna, Austria, August 30 - Sept. 1, 2017 2017 (0) 2017
    Conference paper
    Ralph Görgen, Kim Grüttner, Fernando Herrera, Pablo Peñil, Julio L. Medina, Eugenio Villar, Gianluca Palermo, William Fornaciari, Carlo Brandolese, Davide Gadioli, Sara Bocchio, Luca Ceva, Paolo Azzoni, Massimo Poncino, Sara Vinco, Enrico Macii, Salvatore Cusenza, John M. Favaro, Raúl Valencia, Ingo Sander, Kathrin Rosvall, Davide Quaglia.
    CONTREX: Design of Embedded Mixed-Criticality CONTRol Systems under Consideration of EXtra-Functional Properties.
    2016 Euromicro Conference on Digital System Design, DSD 2016, Limassol, Cyprus, August 31 - September 2, 2016 2016 (0) 2016
    Conference paper
    Héctor Posadas, Eugenio Villar.
    Using Professional Resources for Teaching Embedded SW Development.
    IEEE-RITA 2016, Volume 11 (0) 2016
    Conference paper
    Fernando Herrera, Pablo Peñil, Eugenio Villar.
    A model-based, single-source approach to design-space exploration and synthesis of mixed-criticality systems.
    Proceedings of the 18th International Workshop on Software and Compilers for Embedded Systems, SCOPES 2015, Sankt Goar, Germany, June 1-3, 2015 2015 (0) 2015
    Conference paper
    Fernando Herrera, Pablo Peñil, Eugenio Villar.
    Enhancing analysability and time predictability in UML/MARTE component-based application models.
    2015 Forum on Specification and Design Languages, FDL 2015, Barcelona, Spain, September 14-16, 2015 2015 (0) 2015
    Conference paper
    Héctor Posadas, Pablo Peñil, Alejandro Nicolás, Eugenio Villar.
    Automatic synthesis of communication and concurrency for exploring component-based system implementations considering UML channel semantics.
    Journal of Systems Architecture - Embedded Systems Design 2015, Volume 61 (0) 2015
    Conference paper
    Jiafu Wan, Chin-Feng Lai, Shiwen Mao, Eugenio Villar, Subhas Mukhopadhyay.
    Innovative circuit and system design methodologies for green cyber-physical systems.
    Microprocessors and Microsystems - Embedded Hardware Design 2015, Volume 39 (0) 2015
    Conference paper
    Emad Samuel Malki Ebeid, Franco Fummi, Davide Quaglia, Héctor Posadas, Eugenio Villar.
    A framework for design space exploration and performance analysis of networked embedded systems.
    Proceedings of the 2014 Workshop on Rapid Simulation and Performance Evaluation: Methods and Tools, RAPIDO '14, 22 January, 2014, Vienna, Austria 2014 (0) 2014
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