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    Author information
    First name: Dajiang
    Last name: Zhou
    DBLP: 79/3501
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    Show item 1 to 25 of 92  
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    Conference paper
    Dajiang Zhou, Shihao Wang, Heming Sun, Jian-Bin Zhou, Jiayi Zhu, Yijin Zhao, Jinjia Zhou, Shuping Zhang, Shinji Kimura, Takeshi Yoshimura, Satoshi Goto.
    An 8K H.265/HEVC Video Decoder Chip With a New System Pipeline Design.
    J. Solid-State Circuits 2017, Volume 52 (0) 2017
    Conference paper
    Shihao Wang, Dajiang Zhou, Jian-Bin Zhou, Takeshi Yoshimura, Satoshi Goto.
    VLSI Implementation of HEVC Motion Compensation With Distance Biased Direct Cache Mapping for 8K UHDTV Applications.
    IEEE Trans. Circuits Syst. Video Techn. 2017, Volume 27 (0) 2017
    Journal article
    Zhengxue Cheng, Heming Sun, Dajiang Zhou, Shinji Kimura.
    Accelerating HEVC Inter Prediction with Improved Merge Mode Handling.
    IEICE Transactions 2017, Volume 100 (0) 2017
    Conference paper
    Jinjia Zhou, Dajiang Zhou, Satoshi Goto.
    100x Evolution of Video Codec Chips.
    Proceedings of the 2017 ACM on International Symposium on Physical Design, ISDP 2017, Portland, OR, USA, March 19-22, 2017 2017 (0) 2017
    Conference paper
    Xushen Han, Dajiang Zhou, Shihao Wang, Shinji Kimura.
    CNN-MERP: An FPGA-Based Memory-Efficient Reconfigurable Processor for Forward and Backward Propagation of Convolutional Neural Networks.
    CoRR 2017, Volume 0 (0) 2017
    Conference paper
    Shihao Wang, Dajiang Zhou, Xushen Han, Takeshi Yoshimura.
    Chain-NN: An Energy-Efficient 1D Chain Architecture for Accelerating Deep Convolutional Neural Networks.
    CoRR 2017, Volume 0 (0) 2017
    Conference paper
    Shihao Wang, Dajiang Zhou, Xushen Han, Takeshi Yoshimura.
    Chain-NN: An energy-efficient 1D chain architecture for accelerating deep convolutional neural networks.
    Design, Automation Test in Europe Conference Exhibition, DATE 2017, Lausanne, Switzerland, March 27-31, 2017 2017 (0) 2017
    Conference paper
    Jian-Bin Zhou, Dajiang Zhou, Shihao Wang, Shuping Zhang, Takeshi Yoshimura, Satoshi Goto.
    A Dual-Clock VLSI Design of H.265 Sample Adaptive Offset Estimation for 8k Ultra-HD TV Encoding.
    IEEE Trans. VLSI Syst. 2017, Volume 25 (0) 2017
    Conference paper
    Dajiang Zhou, Shihao Wang, Heming Sun, Jian-Bin Zhou, Jiayi Zhu, Yijin Zhao, Jinjia Zhou, Shuping Zhang, Shinji Kimura, Takeshi Yoshimura, Satoshi Goto.
    14.7 A 4Gpixel/s 8/10b H.265/HEVC video decoder chip for 8K Ultra HD applications.
    2016 IEEE International Solid-State Circuits Conference, ISSCC 2016, San Francisco, CA, USA, January 31 - February 4, 2016 2016 (0) 2016
    Conference paper
    Li Guo 0006, Dajiang Zhou, Shinji Kimura, Satoshi Goto.
    Frame-level quality and memory traffic allocation for lossy embedded compression in video codec systems.
    CoRR 2016, Volume 0 (0) 2016
    Conference paper
    Zhenqi Wei, Peilin Liu, Rongdi Sun, Zunquan Zhou, Ke Jin, Dajiang Zhou.
    HyDMA: low-latency inter-core DMA based on a hybrid packet-circuit switching network-on-chip.
    IEICE Electronic Express 2016, Volume 13 (0) 2016
    Conference paper
    Li Guo 0006, Dajiang Zhou, Shinji Kimura, Satoshi Goto.
    Frame-level quality and memory traffic allocation for lossy embedded compression in video codec systems.
    2016 IEEE International Conference on Multimedia Expo Workshops, ICME Workshops 2016, Seattle, WA, USA, July 11-15, 2016 2016 (0) 2016
    Conference paper
    Xushen Han, Dajiang Zhou, Shihao Wang, Shinji Kimura.
    CNN-MERP: An FPGA-based memory-efficient reconfigurable processor for forward and backward propagation of convolutional neural networks.
    34th IEEE International Conference on Computer Design, ICCD 2016, Scottsdale, AZ, USA, October 2-5, 2016 2016 (0) 2016
    Conference paper
    Heming Sun, Dajiang Zhou, Shuping Zhang, Shinji Kimura.
    A Low-Power VLSI Architecture for HEVC De-Quantization and Inverse Transform.
    IEICE Transactions 2016, Volume 99 (0) 2016
    Conference paper
    Dajiang Zhou, Jinjia Zhou, Wei Fei, Satoshi Goto.
    Ultra-High-Throughput VLSI Architecture of H.265/HEVC CABAC Encoder for UHDTV Applications.
    IEEE Trans. Circuits Syst. Video Techn. 2015, Volume 25 (0) 2015
    Conference paper
    Shuping Zhang, Jinjia Zhou, Dajiang Zhou, Shinji Kimura, Satoshi Goto.
    Low-Power Motion Estimation Processor with 3D Stacked Memory.
    IEICE Transactions 2015, Volume 98 (0) 2015
    Conference paper
    Shihao Wang, Dajiang Zhou, Jian-Bin Zhou, Takeshi Yoshimura, Satoshi Goto.
    Unified Parameter Decoder Architecture for H.265/HEVC Motion Vector and Boundary Strength Decoding.
    IEICE Transactions 2015, Volume 98 (0) 2015
    Conference paper
    Landan Hu, Heming Sun, Dajiang Zhou, Shinji Kimura.
    Hardware-oriented rate-distortion optimization algorithm for HEVC intra-frame encoder.
    2015 IEEE International Conference on Multimedia Expo Workshops, ICME Workshops 2015, Turin, Italy, June 29 - July 3, 2015 2015 (0) 2015
    Conference paper
    Jinjia Zhou, Yizhou Zou, Dajiang Zhou, Satoshi Goto.
    A fixed-complexity HEVC inter mode filtering algorithm based on distribution of IME-FME cost ratio.
    2015 IEEE International Symposium on Circuits and Systems, ISCAS 2015, Lisbon, Portugal, May 24-27, 2015 2015 (0) 2015
    Conference paper
    Jiayi Zhu, Li Guo, Dajiang Zhou, Shinji Kimura, Satoshi Goto.
    An independent bandwidth reduction device for HEVC VLSI video system.
    2015 IEEE International Symposium on Circuits and Systems, ISCAS 2015, Lisbon, Portugal, May 24-27, 2015 2015 (0) 2015
    Conference paper
    Gang He, Dajiang Zhou, Yunsong Li, Zhixiang Chen, Tianruo Zhang, Satoshi Goto.
    High-Throughput Power-Efficient VLSI Architecture of Fractional Motion Estimation for Ultra-HD HEVC Video Encoding.
    IEEE Trans. VLSI Syst. 2015, Volume 23 (0) 2015
    Conference paper
    Jinjia Zhou, Dajiang Zhou, Jiayi Zhu, Satoshi Goto.
    A Frame-Parallel 2 Gpixel/s Video Decoder Chip for UHDTV and 3-DTV/FTV Applications.
    IEEE Trans. VLSI Syst. 2015, Volume 23 (0) 2015
    Conference paper
    Jian-Bin Zhou, Dajiang Zhou, Shihao Wang, Takeshi Yoshimura, Satoshi Goto.
    High Performance VLSI Architecture of H.265/HEVC Intra Prediction for 8K UHDTV Video Decoder.
    IEICE Transactions 2015, Volume 98 (0) 2015
    Conference paper
    Zhengxue Cheng, Heming Sun, Dajiang Zhou, Shinji Kimura.
    Merge mode based fast inter prediction for HEVC.
    2015 Visual Communications and Image Processing, VCIP 2015, Singapore, December 13-16, 2015 2015 (0) 2015
    Conference paper
    Zhe Sheng, Dajiang Zhou, Heming Sun, Satoshi Goto.
    Low-Complexity Rate-Distortion Optimization Algorithms for HEVC Intra Prediction.
    MultiMedia Modeling - 20th Anniversary International Conference, MMM 2014, Dublin, Ireland, January 6-10, 2014, Proceedings, Part I 2014 (0) 2014
    Show item 1 to 25 of 92  

    Your query returned 92 matches in the database.