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    First name: Shigeru
    Last name: Yamashita
    DBLP: 84/878
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    Journal article
    Nurul Ain Binti Adnan, Shigeru Yamashita, Alan Mishchenko.
    Reduction of Quantum Cost by Making Temporary Changes to the Function.
    IEICE Transactions 2017, Volume 100 (0) 2017
    Journal article
    Ritsuko Muguruma, Shigeru Yamashita.
    Stochastic Number Generation with the Minimum Inputs.
    IEICE Transactions 2017, Volume 100 (0) 2017
    Journal article
    Takahiro Yamamoto, Ittetsu Taniguchi, Hiroyuki Tomiyama, Shigeru Yamashita, Yuko Hara-Azumi.
    A Systematic Methodology for Design and Worst-Case Error Analysis of Approximate Array Multipliers.
    IEICE Transactions 2017, Volume 100 (0) 2017
    Conference paper
    Trung Anh Dinh, Shigeru Yamashita, Tsung-Yi Ho.
    A Full-Flexibility-Guaranteed Pin-Count Reduction Design for General-Purpose Digital Microfluidic Biochips.
    IEICE Transactions 2016, Volume 99 (0) 2016
    Conference paper
    Ritsuko Muguruma, Shigeru Yamashita.
    Stochastic Number Generation with Few Inputs.
    29th International Conference on VLSI Design and 15th International Conference on Embedded Systems, VLSID 2016, Kolkata, India, January 4-8, 2016 2016 (0) 2016
    Conference paper
    Abhimanyu Yadav, Trung Anh Dinh, Daiki Kitagawa, Shigeru Yamashita.
    ILP-based Synthesis for Sample Preparation Applications on Digital Microfluidic Biochips.
    29th International Conference on VLSI Design and 15th International Conference on Embedded Systems, VLSID 2016, Kolkata, India, January 4-8, 2016 2016 (0) 2016
    Conference paper
    Tsung-Yi Ho, Shigeru Yamashita, Ansuman Banerjee, Sudip Roy 0001.
    Design of Microfluidic Biochips: Connecting Algorithms and Foundations of Chip Design to Biochemistry and the Life Sciences.
    29th International Conference on VLSI Design and 15th International Conference on Embedded Systems, VLSID 2016, Kolkata, India, January 4-8, 2016 2016 (0) 2016
    Conference paper
    Jason Helge Anderson, Yuko Hara-Azumi, Shigeru Yamashita.
    Effect of LFSR seeding, scrambling and feedback polynomial on stochastic computing accuracy.
    2016 Design, Automation Test in Europe Conference Exhibition, DATE 2016, Dresden, Germany, March 14-18, 2016 2016 (0) 2016
    Conference paper
    Nurul Ain Binti Adnan, Kouhei Kushida, Shigeru Yamashita.
    A pre-optimization technique to generate initial reversible circuits with low quantum cost.
    IEEE International Symposium on Circuits and Systems, ISCAS 2016, Montréal, QC, Canada, May 22-25, 2016 2016 (0) 2016
    Conference paper
    Takahiro Yamamoto, Ittetsu Taniguchi, Hiroyuki Tomiyama, Shigeru Yamashita, Yuko Hara-Azumi.
    A systematic methodology for design and analysis of approximate array multipliers.
    2016 IEEE Asia Pacific Conference on Circuits and Systems, APCCAS 2016, Jeju, South Korea, October 25-28, 2016 2016 (0) 2016
    Conference paper
    Andris Ambainis, Kazuo Iwama, Masaki Nakanishi, Harumichi Nishimura, Raymond H. Putra, Seiichiro Tani, Shigeru Yamashita.
    Quantum Query Complexity of Almost All Functions with Fixed On-set Size.
    Computational Complexity 2016, Volume 25 (0) 2016
    Conference paper
    Trung Anh Dinh, Shigeru Yamashita, Tsung-Yi Ho.
    An Optimal Pin-Count Design With Logic Optimization for Digital Microfluidic Biochips.
    IEEE Trans. on CAD of Integrated Circuits and Systems 2015, Volume 34 (0) 2015
    Conference paper
    Trung Anh Dinh, Shigeru Yamashita, Tsung-Yi Ho, Krishnendu Chakrabarty.
    Testing of digital microfluidic biochips with arbitrary layouts.
    20th IEEE European Test Symposium, ETS 2015, Cluj-Napoca, Romania, 25-29 May, 2015 2015 (0) 2015
    Conference paper
    Trung Anh Dinh, Shigeru Yamashita, Tsung-Yi Ho, Krishnendu Chakrabarty.
    A general testing method for digital microfluidic biochips under physical constraints.
    2015 IEEE International Test Conference, ITC 2015, Anaheim, CA, USA, October 6-8, 2015 2015 (0) 2015
    Conference paper
    Trung Anh Dinh, Shigeru Yamashita, Tsung-Yi Ho.
    A network-flow-based optimal sample preparation algorithm for digital microfluidic biochips.
    19th Asia and South Pacific Design Automation Conference, ASP-DAC 2014, Singapore, January 20-23, 2014 2014 (0) 2014
    Conference paper
    Trung Anh Dinh, Shigeru Yamashita, Tsung-Yi Ho.
    A logic integrated optimal pin-count design for digital microfluidic biochips.
    Design, Automation Test in Europe Conference Exhibition, DATE 2014, Dresden, Germany, March 24-28, 2014 2014 (0) 2014
    Conference paper
    Nurul Ain Binti Adnan, Shigeru Yamashita, Simon J. Devitt, Kae Nemoto.
    2D Qubit Layout Optimization for Topological Quantum Computation.
    Reversible Computation - 6th International Conference, RC 2014, Kyoto, Japan, July 10-11, 2014. Proceedings 2014 (0) 2014
    Conference paper
    Shunichi Sanae, Yuko Hara-Azumi, Shigeru Yamashita, Yasuhiko Nakashima.
    Better-Than-DMR Techniques for Yield Improvement.
    22nd IEEE Annual International Symposium on Field-Programmable Custom Computing Machines, FCCM 2014, Boston, MA, USA, May 11-13, 2014 2014 (0) 2014
    Conference paper
    Hiroaki Yoshida, Masayuki Wakizaka, Shigeru Yamashita, Masahiro Fujita.
    An Energy-Efficient Patchable Accelerator and Its Design Methods.
    IEICE Transactions 2014, Volume 97 (0) 2014
    Journal article
    Marcos Villagra, Masaki Nakanishi, Shigeru Yamashita, Yasuhiko Nakashima.
    Tensor Rank and Strong Quantum Nondeterminism in Multiparty Communication.
    IEICE Transactions 2013, Volume 96 (0) 2013
    Conference paper
    Trung Anh Dinh, Shigeru Yamashita, Tsung-Yi Ho, Yuko Hara-Azumi.
    A clique-based approach to find binding and scheduling result in flow-based microfluidic biochips.
    18th Asia and South Pacific Design Automation Conference, ASP-DAC 2013, Yokohama, Japan, January 22-25, 2013 2013 (0) 2013
    Conference paper
    Tanvir Ahmed, Jun Yao, Yuko Hara-Azumi, Shigeru Yamashita, Yasuhiko Nakashima.
    Selective Check of Data-Path for Effective Fault Tolerance.
    IEICE Transactions 2013, Volume 96 (0) 2013
    Conference paper
    Trung Anh Dinh, Shigeru Yamashita, Tsung-Yi Ho, Yuko Hara-Azumi.
    Clique-Based Architectural Synthesis of Flow-Based Microfluidic Biochips.
    IEICE Transactions 2013, Volume 96 (0) 2013
    Journal article
    Shigeru Yamashita, Shin-ichi Minato, D. Michael Miller.
    Synthesis of Semi-Classical Quantum Circuits.
    Multiple-Valued Logic and Soft Computing 2012, Volume 18 (0) 2012
    Conference paper
    Marcos Villagra, Masaki Nakanishi, Shigeru Yamashita, Yasuhiko Nakashima.
    Quantum Walks on the Line with Phase Parameters.
    IEICE Transactions 2012, Volume 95 (0) 2012
    Conference paper
    Marcos Villagra, Masaki Nakanishi, Shigeru Yamashita, Yasuhiko Nakashima.
    Tensor Rank and Strong Quantum Nondeterminism in Multiparty Communication.
    Theory and Applications of Models of Computation - 9th Annual Conference, TAMC 2012, Beijing, China, May 16-21, 2012. Proceedings 2012 (0) 2012
    Conference paper
    Richard Cleve, Kazuo Iwama, François Le Gall, Harumichi Nishimura, Seiichiro Tani, Junichi Teruyama, Shigeru Yamashita.
    Reconstructing Strings from Substrings with Quantum Queries.
    Algorithm Theory - SWAT 2012 - 13th Scandinavian Symposium and Workshops, Helsinki, Finland, July 4-6, 2012. Proceedings 2012 (0) 2012
    Conference paper
    Richard Cleve, Kazuo Iwama, François Le Gall, Harumichi Nishimura, Seiichiro Tani, Junichi Teruyama, Shigeru Yamashita.
    Reconstructing Strings from Substrings with Quantum Queries
    CoRR 2012, Volume 0 (0) 2012
    Conference paper
    Marcos Villagra, Masaki Nakanishi, Shigeru Yamashita, Yasuhiko Nakashima.
    Tensor Rank and Strong Quantum Nondeterminism in Multiparty Communication
    CoRR 2012, Volume 0 (0) 2012
    Conference paper
    Shigeru Yamashita.
    An Optimization Problem for Topological Quantum Computation.
    21st IEEE Asian Test Symposium, ATS 2012, Niigata, Japan, November 19-22, 2012 2012 (0) 2012
    Conference paper
    Marcos Villagra, Masaki Nakanishi, Shigeru Yamashita, Yasuhiko Nakashima.
    Tensor Rank and Strong Quantum Nondeterminism in Multiparty Communication.
    Electronic Colloquium on Computational Complexity (ECCC) 2012, Volume 19 (0) 2012
    Conference paper
    Masayuki Wakizaka, Hiroaki Yoshida, Yuko Hara-Azumi, Shigeru Yamashita.
    A redundant wire addition method for Patchable Accelerator.
    19th IEEE International Conference on Electronics, Circuits and Systems, ICECS 2012, Seville, Spain, December 9-12, 2012 2012 (0) 2012
    Conference paper
    Hratch Mangassarian, Hiroaki Yoshida, Andreas G. Veneris, Shigeru Yamashita, Masahiro Fujita.
    On error tolerance and Engineering Change with Partially Programmable Circuits.
    Proceedings of the 17th Asia and South Pacific Design Automation Conference, ASP-DAC 2012, Sydney, Australia, January 30 - February 2, 2012 2012 (0) 2012
    Conference paper
    Yuichi Hirata, Masaki Nakanishi, Shigeru Yamashita, Yasuhiko Nakashima.
    An efficient conversion of quantum circuits to a linear nearest neighbor architecture.
    Quantum Information Computation 2011, Volume 11 (0) 2011
    Conference paper
    Hiroshi Aoki, Shigeru Yamashita, Shin-ichi Minato.
    An efficient algorithm for constructing a Sequence Binary Decision Diagram representing a set of reversed sequences.
    2011 IEEE International Conference on Granular Computing, GrC-2011, Kaohsiung, Taiwan, November 8-10, 2011 2011 (0) 2011
    Conference paper
    Atsushi Matsuo, Shigeru Yamashita.
    Changing the Gate Order for Optimal LNN Conversion.
    Reversible Computation - Third International Workshop, RC 2011, Gent, Belgium, July 4-5, 2011. Revised Papers 2012 (0) 2011
    Journal article
    Shigeru Yamashita, Igor L. Markov.
    Fast equivalence - checking for quantum circuits.
    Quantum Information Computation 2010, Volume 10 (0) 2010
    Conference paper
    Shigeru Yamashita, Igor L. Markov.
    Fast equivalence-checking for quantum circuits.
    2010 IEEE/ACM International Symposium on Nanoscale Architectures, NANOARCH 2010, Anaheim, CA, USA, June 17-18, 2010 2010 (0) 2010
    Journal article
    Yumi Nakajima, Yasuhito Kawano, Hiroshi Sekigawa, Masaki Nakanishi, Shigeru Yamashita, Yasuhiko Nakashima.
    Synthesis of quantum circuits for d-level systems by using cosine-sine decomposition.
    Quantum Information Computation 2009, Volume 9 (0) 2009
    Conference paper
    Shigeru Yamashita, Igor L. Markov.
    Fast Equivalence-checking for Quantum Circuits.
    CoRR 2009, Volume 0 (0) 2009
    Conference paper
    Andris Ambainis, Kazuo Iwama, Masaki Nakanishi, Harumichi Nishimura, Rudy Raymond, Seiichiro Tani, Shigeru Yamashita.
    Average/Worst-Case Gap of Quantum Query Complexities by On-Set Size
    CoRR 2009, Volume 0 (0) 2009
    Conference paper
    Seiichiro Tani, Masaki Nakanishi, Shigeru Yamashita.
    Multi-Party Quantum Communication Complexity with Routed Messages.
    IEICE Transactions 2009, Volume 92 (0) 2009
    Conference paper
    Shigeru Yamashita, Shin-ichi Minato, D. Michael Miller.
    An efficient verification of quantum circuits under a practical restriction.
    Proceedings of 8th IEEE International Conference on Computer and Information Technology, CIT 2008, Sydney, Australia, July 8-11, 2008 2008 (0) 2008
    Conference paper
    Seiichiro Tani, Masaki Nakanishi, Shigeru Yamashita.
    Multi-party Quantum Communication Complexity with Routed Messages.
    Computing and Combinatorics, 14th Annual International Conference, COCOON 2008, Dalian, China, June 27-29, 2008, Proceedings 2008 (0) 2008
    Conference paper
    Kazuo Iwama, Harumichi Nishimura, Mike Paterson, Rudy Raymond, Shigeru Yamashita.
    Polynomial-Time Construction of Linear Network Coding.
    Automata, Languages and Programming, 35th International Colloquium, ICALP 2008, Reykjavik, Iceland, July 7-11, 2008, Proceedings, Part I: Tack A: Algorithms, Automata, Complexity, and Games 2008 (0) 2008
    Conference paper
    Andris Ambainis, Kazuo Iwama, Masaki Nakanishi, Harumichi Nishimura, Rudy Raymond, Seiichiro Tani, Shigeru Yamashita.
    Quantum Query Complexity of Boolean Functions with Small On-Sets.
    Algorithms and Computation, 19th International Symposium, ISAAC 2008, Gold Coast, Australia, December 15-17, 2008. Proceedings 2008 (0) 2008
    Conference paper
    Shigeru Yamashita, Shin-ichi Minato, D. Michael Miller.
    DDMF: An Efficient Decision Diagram Structure for Design Verification of Quantum Circuits under a Practical Restriction.
    IEICE Transactions 2008, Volume 91 (0) 2008
    Conference paper
    K. Suzuki, T. Nakada, Masaki Nakanishi, Shigeru Yamashita, Yasuhiko Nakashima.
    A Functional Unit with Small Variety of Highly Reliable Cells.
    14th IEEE Pacific Rim International Symposium on Dependable Computing, PRDC 2008, 15-17 December 2008, Taipei, Taiwan 2008 (0) 2008
    Conference paper
    Kazuo Iwama, Harumichi Nishimura, Rudy Raymond, Shigeru Yamashita.
    Unbounded-Error One-Way Classical and Quantum Communication Complexity.
    Automata, Languages and Programming, 34th International Colloquium, ICALP 2007, Wroclaw, Poland, July 9-13, 2007, Proceedings 2007 (0) 2007
    Conference paper
    Kazuo Iwama, Harumichi Nishimura, Rudy Raymond, Shigeru Yamashita.
    Unbounded-Error Classical and Quantum Communication Complexity.
    Algorithms and Computation, 18th International Symposium, ISAAC 2007, Sendai, Japan, December 17-19, 2007, Proceedings 2007 (0) 2007
    Conference paper
    Masahito Hayashi, Kazuo Iwama, Harumichi Nishimura, Raymond H. Putra, Shigeru Yamashita.
    Quantum Network Coding.
    STACS 2007, 24th Annual Symposium on Theoretical Aspects of Computer Science, Aachen, Germany, February 22-24, 2007, Proceedings 2007 (0) 2007
    Conference paper
    Shinya Hiramoto, Masaki Nakanishi, Shigeru Yamashita, Yasuhiko Nakashima.
    A Hardware SAT Solver Using Non-chronological Backtracking and Clause Recording Without Overheads.
    Reconfigurable Computing: Architectures, Tools and Applications, Third International Workshop, ARC 2007, Mangaratiba, Brazil, March 27-29, 2007. 2007 (0) 2007
    Conference paper
    Shigeru Yamashita, Masaki Nakanishi.
    A practical framework to utilize quantum search.
    Proceedings of the IEEE Congress on Evolutionary Computation, CEC 2007, 25-28 September 2007, Singapore 2007 (0) 2007
    Conference paper
    Tomoya Suzuki, Shigeru Yamashita, Masaki Nakanishi, Katsumasa Watanabe.
    Robust Quantum Algorithms Computing OR with epsilon-Biased Oracles.
    IEICE Transactions 2007, Volume 90 (0) 2007
    Conference paper
    Andris Ambainis, Kazuo Iwama, Akinori Kawachi, Rudy Raymond, Shigeru Yamashita.
    Improved algorithms for quantum identification of Boolean oracles.
    Theor. Comput. Sci. 2007, Volume 378 (0) 2007
    Conference paper
    Shigeru Yamashita, Katsunori Tanaka, Hideyuki Takada, Koji Obata, Kazuyoshi Takagi.
    A transduction-based framework to synthesize RSFQ circuits.
    Proceedings of the 2006 Conference on Asia South Pacific Design Automation: ASP-DAC 2006, Yokohama, Japan, January 24-27, 2006 2006 (0) 2006
    Conference paper
    Tomoya Suzuki, Shigeru Yamashita, Masaki Nakanishi, Katsumasa Watanabe.
    Robust Quantum Algorithms with
    Computing and Combinatorics, 12th Annual International Conference, COCOON 2006, Taipei, Taiwan, August 15-18, 2006, Proceedings 2006 (0) 2006
    Conference paper
    Masahito Hayashi, Kazuo Iwama, Harumichi Nishimura, Rudy Raymond, Shigeru Yamashita.
    Quantum Network Coding.
    Complexity of Boolean Functions, 12.03. - 17.03.2006 2006 (0) 2006
    Conference paper
    Andris Ambainis, Kazuo Iwama, Akinori Kawachi, Raymond H. Putra, Shigeru Yamashita.
    Improved Algorithms for Quantum Identification of Boolean Oracles.
    Algorithm Theory - SWAT 2006, 10th ScandinavianWorkshop on Algorithm Theory, Riga, Latvia, July 6-8, 2006, Proceedings 2006 (0) 2006
    Conference paper
    Mitsuru Tomono, Masaki Nakanishi, Shigeru Yamashita, Kazuo Nakajima, Katsumasa Watanabe.
    An Efficient and Effective Algorithm for Online Task Placement with I/O Communications in Partially Reconfigurable FPGAs.
    IEICE Transactions 2006, Volume 89 (0) 2006
    Conference paper
    Mark Adcock, Richard Cleve, Kazuo Iwama, Raymond H. Putra, Shigeru Yamashita.
    Quantum lower bounds for the Goldreich-Levin problem.
    Inf. Process. Lett. 2006, Volume 97 (0) 2006
    Conference paper
    Mitsuru Tomono, Masaki Nakanishi, Katsumasa Watanabe, Shigeru Yamashita.
    Event-oriented computing with reconfigurable platform.
    Proceedings of the 2005 Conference on Asia South Pacific Design Automation, ASP-DAC 2005, Shanghai, China, January 18-21, 2005 2005 (0) 2005
    Conference paper
    Nobuo Nakai, Masaki Nakanishi, Shigeru Yamashita, Katsumasa Watanabe.
    Reconfigurable 1-Bit Processor Array with Reduced Wirng Area.
    Proceedings of The 2005 International Conference on Engineering of Reconfigurable Systems and Algorithms, ERSA 2005, Las Vegas, Nevada, USA, June 27-30, 2005 2005 (0) 2005
    Conference paper
    Kazuo Iwama, Akinori Kawachi, Shigeru Yamashita.
    Quantum Sampling for Balanced Allocations.
    IEICE Transactions 2005, Volume 88 (0) 2005
    Conference paper
    Katsunori Tanaka, Shigeru Yamashita, Yahiko Kambayashi.
    SPFD-Based Flexible Transformation of LUT-Based FPGA Circuits.
    IEICE Transactions 2005, Volume 88 (0) 2005
    Conference paper
    Katsunori Tanaka, Shigeru Yamashita, Yahiko Kambayashi.
    SPFD-based one-to-many rewiring.
    Proceedings of the ACM/SIGDA 12th International Symposium on Field Programmable Gate Arrays, FPGA 2004, Monterey, California, USA, February 22-24, 2004 2004 (0) 2004
    Conference paper
    Katsunori Tanaka, Shigeru Yamashita, Yahiko Kambayashi.
    SPFD-based effective one-to-many rewiring (OMR) for delay reduction of LUT-based FPGA circuits.
    Proceedings of the 14th ACM Great Lakes Symposium on VLSI 2004, Boston, MA, USA, April 26-28, 2004 2004 (0) 2004
    Conference paper
    Andris Ambainis, Kazuo Iwama, Akinori Kawachi, Hiroyuki Masuda, Raymond H. Putra, Shigeru Yamashita.
    Quantum Identification of Boolean Oracles.
    STACS 2004, 21st Annual Symposium on Theoretical Aspects of Computer Science, Montpellier, France, March 25-27, 2004, Proceedings 2004 (0) 2004
    Conference paper
    Kazuo Iwama, Akinori Kawachi, Shigeru Yamashita.
    Quantum Sampling for Balanced Allocations.
    Computing and Combinatorics, 9th Annual International Conference, COCOON 2003, Big Sky, MT, USA, July 25-28, 2003, Proceedings 2003 (0) 2003
    Conference paper
    Kazuo Iwama, Shigeru Yamashita.
    Transformation Rules for CNOT-based Quantum Circuits and Their Applications.
    New Generation Comput. 2002, Volume 21 (0) 2003
    Conference paper
    Noboru Kunihiro, Shigeru Yamashita.
    Efficient Algorithms for NMR Quantum Computers with Small Qubits.
    New Generation Comput. 2002, Volume 21 (0) 2003
    Conference paper
    Kazuo Iwama, Yahiko Kambayashi, Shigeru Yamashita.
    Transformation rules for designing CNOT-based quantum circuits.
    Proceedings of the 39th Design Automation Conference, DAC 2002, New Orleans, LA, USA, June 10-14, 2002 2002 (0) 2002
    Conference paper
    Shigeru Yamashita, Hiroshi Sawada, Akira Nagoya.
    An efficient framework of using various decomposition methods to synthesize LUT networks and its evaluation.
    Proceedings of ASP-DAC 2000, Asia and South Pacific Design Automation Conference 2000, Yokohama, Japan 2000 (0) 2000
    Conference paper
    Shigeru Yamashita, Hiroshi Sawada, Akira Nagoya.
    SPFD: A new method to express functional flexibility.
    IEEE Trans. on CAD of Integrated Circuits and Systems 2000, Volume 19 (0) 2000
    Conference paper
    Shigeru Yamashita, Hiroshi Sawada, Akira Nagoya.
    An Integrated Approach for Synthesizing LUT Networks.
    9th Great Lakes Symposium on VLSI (GLS-VLSI '99), 4-6 March 1999, Ann Arbor, MI, USA 1999 (0) 1999
    Conference paper
    Shigeru Yamashita, Hiroshi Sawada, Akira Nagoya.
    New Methods to Find Optimal Non-Disjoint Bi-Decompositions.
    ASP-DAC 1998 (0) 1998
    Conference paper
    Hiroshi Sawada, Shigeru Yamashita, Akira Nagoya.
    Restructuring Logic Representations with Easily Detectable Simple Disjunctive Decompositions.
    1998 Design, Automation and Test in Europe (DATE '98), February 23-26, 1998, Le Palais des Congrès de Paris, Paris, France 1998 (0) 1998
    Conference paper
    Hiroshi Sawada, Shigeru Yamashita, Akira Nagoya.
    Restricted Simple Disjunctive Decompositions Based on Grouping Symmetric Variables.
    7th Great Lakes Symposium on VLSI (GLS-VLSI '97), 13-15 March 1997, Urbana, IL, USA 1997 (0) 1997
    Journal article
    Shigeru Yamashita, Yahiko Kambayashi, Saburo Muroga.
    Optimization methods for look-up table-type FPGAs based on permissible functions.
    Systems and Computers in Japan 1996, Volume 27 (0) 1996
    Journal article
    Shigeru Yamashita, Yahiko Kambayashi, Saburo Muroga.
    Design of logic circuits with wired-logic utilizing transduction method.
    Systems and Computers in Japan 1996, Volume 27 (0) 1996
    Conference paper
    Shigeru Yamashita, Hiroshi Sawada, Akira Nagoya.
    A new method to express functional permissibilities for LUT based FPGAs and its applications.
    ICCAD 1996 (0) 1996
    Conference paper
    Shigeru Yamashita, Yahiko Kambayashi, Saburo Muroga.
    Optimization methods for lookup-table-based FPGAs using transduction method.
    Proceedings of the 1995 Conference on Asia Pacific Design Automation, Makuhari, Massa, Chiba, Japan, August 29 - September 1, 1995 1995 (0) 1995
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