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First name:	Yeong-Jar
Last name:	Chang
DBLP:	87/4590
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	Conference paper Yu-Shih Su, Wing-Kai Hon, Cheng-Chih Yang, Shih-Chieh Chang, Yeong-Jar Chang. Clock Skew Minimization in Multi-Voltage Mode Designs Using Adjustable Delay Buffers.	IEEE Trans. on CAD of Integrated Circuits and Systems 2010, Volume 29	(0)	2010
	Conference paper Yu-Shih Su, Wing-Kai Hon, Cheng-Chih Yang, Shih-Chieh Chang, Yeong-Jar Chang. Value assignment of adjustable delay buffers for clock skew minimization in multi-voltage mode designs.	2009 International Conference on Computer-Aided Design (ICCAD'09), November 2-5, 2009, San Jose, CA, USA 2009	(0)	2009
	Conference paper Ming-Dou Ker, Po-Yen Chiu, Fu-Yi Tsai, Yeong-Jar Chang. On the Design of Power-rail ESD Clamp Circuit with Consideration of Gate Leakage Current in 65-nm Low-voltage CMOS Process.	International Symposium on Circuits and Systems (ISCAS 2009), 24-17 May 2009, Taipei, Taiwan 2009	(0)	2009
	Conference paper Chung-Fu Lin, Chia-Fu Huang, De-Chung Lu, Chih-Chiang Hsu, Wen-Tsung Chiu, Yu-Wei Chen, Yeong-Jar Chang. A Low-Cost Programmable Memory BIST Design for Multiple Memory Instances.	2008 IEEE International Test Conference, ITC 2008, Santa Clara, California, USA, October 26-31, 2008 2008	(0)	2008
	Conference paper Ming Shae Wu, Chung-Len Lee, Yeong-Jar Chang, Wen Ching Wu. Crosstalk Fault Detection for Interconnection Lines Based on Path Delay Inertia Principle.	14th Asian Test Symposium (ATS 2005), 18-21 December 2005, Calcutta, India 2005	(0)	2005
	Conference paper Rei-Fu Huang, Chin-Lung Su, Cheng-Wen Wu, Shen-Tien Lin, Kun-Lun Luo, Yeong-Jar Chang. Fail Pattern Identification for Memory Built-In Self-Repair.	13th Asian Test Symposium (ATS 2004), 15-17 November 2004, Kenting, Taiwan 2004	(0)	2004
	Conference paper Chin-Lung Su, Rei-Fu Huang, Cheng-Wen Wu, Chien-Chung Hung, Ming-Jer Kao, Yeong-Jar Chang, Wen Ching Wu. MRAM Defect Analysis and Fault Modeli.	Proceedings 2004 International Test Conference (ITC 2004), October 26-28, 2004, Charlotte, NC, USA 2003	(0)	2004
	Conference paper Li-Ming Denq, Rei-Fu Huang, Cheng-Wen Wu, Yeong-Jar Chang, Wen Ching Wu. A Parallel Built-in Diagnostic Scheme for Multiple Embedded Memories.	12th IEEE International Workshop on Memory Technology, Design, and Testing (MTDT 2004), 9-10 August 2004, San Jose, CA, USA 2004	(0)	2004
	Conference paper Yeong-Jar Chang, Chung-Len Lee, Jwu E. Chen, Chauchin Su. A Behavior-Level Fault Model for the Closed-Loop Operational Amplifier.	J. Inf. Sci. Eng. 2000, Volume 16	(0)	2000
	Conference paper Yeong-Jar Chang, Chung-Len Lee. Synthesis of Multi-Variable MVL Funtions Using Hybrid Mode CMOS Logic.	ISMVL 1994	(0)	1994

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