Publications
Search

Publications :: Search

Show author

On this page you see the details of the selected author.

    Author information
    First name: Yuanwu
    Last name: Lei
    DBLP: 89/1147
    Rating: (not rated yet)
    Bookmark:

    Below you find the publications which have been written by this author.

    Show item 1 to 29 of 29  
    Select a publication
    Show Title Venue Rating Date
    Conference paper
    Baozhou Zhu, Yuanwu Lei, Yuanxi Peng, Tingting He.
    Low Latency and Low Error Floating-Point Sine/Cosine Function Based TCORDIC Algorithm.
    IEEE Trans. on Circuits and Systems 2017, Volume 64 (0) 2017
    Conference paper
    Peng Qiao, Teng Li, Yong Dou, Yuanwu Lei, Hongbing Luo, Chi Jin.
    Platform-Adaptive High-Throughput Surveillance Video Condensation on Heterogeneous Processor Clusters.
    Advanced Parallel Processing Technologies - 12th International Symposium, APPT 2017, Santiago de Compostela, Spain, August 29, 2017, Proceedings 2017 (0) 2017
    Conference paper
    Yueqing Wang, Zhige Xie, Kai Xu 0004, Yong Dou, Yuanwu Lei.
    An efficient and effective convolutional auto-encoder extreme learning machine network for 3d feature learning.
    Neurocomputing 2016, Volume 174 (0) 2016
    Conference paper
    Yueqing Wang, Yong Dou, Xinwang Liu, Yuanwu Lei.
    PR-ELM: Parallel regularized extreme learning machine based on cluster.
    Neurocomputing 2016, Volume 173 (0) 2016
    Conference paper
    Qi Lv, Xin Niu, Yong Dou, Jiaqing Xu, Yuanwu Lei.
    Classification of Hyperspectral Remote Sensing Image Using Hierarchical Local-Receptive-Field-Based Extreme Learning Machine.
    IEEE Geosci. Remote Sensing Lett. 2016, Volume 13 (0) 2016
    Conference paper
    Xiaowen Chen, Zhonghai Lu, Yuanwu Lei, Yaohua Wang, Shenggang Chen.
    Multi-bit transient fault control for NoC links using 2D fault coding method.
    Tenth IEEE/ACM International Symposium on Networks-on-Chip, NOCS 2016, Nara, Japan, August 31 - September 2, 2016 2016 (0) 2016
    Conference paper
    Song Guo, Yong Dou, Yuanwu Lei, Rongchun Li, Yu Li.
    An efficient multi-standard QC-LDPC decoder based on the row-layered decoding algorithm.
    IEICE Electronic Express 2015, Volume 12 (0) 2015
    Conference paper
    Song Guo, Yong Dou, Yuanwu Lei, Guiming Wu.
    A deeply-pipelined FPGA-based SpMV accelerator with a hardware-friendly storage scheme.
    IEICE Electronic Express 2015, Volume 12 (0) 2015
    Conference paper
    Yueqing Wang, Yong Dou, Song Guo, Yuanwu Lei, Dan Zou.
    CPU-GPU hybrid parallel strategy for cosmological simulations.
    Concurrency and Computation: Practice and Experience 2014, Volume 26 (0) 2014
    Conference paper
    Yuanwu Lei, Lei Guo, Yong Dou, Sheng Ma, Jinbo Xu.
    FPGA Implementation of a Special-Purpose VLIW Structure for Double-Precision Elementary Function.
    TRETS 2014, Volume 7 (0) 2014
    Conference paper
    Lei Guo, Yuhua Tang, Yuanwu Lei, Yong Dou, Jie Zhou.
    Transpose-free variable-size FFT accelerator based on-chip SRAM.
    IEICE Electronic Express 2014, Volume 11 (0) 2014
    Journal article
    Yuanwu Lei, Yong Dou, Yazhuo Dong, Jie Zhou, Fei Xia.
    FPGA implementation of an exact dot product and its application in variable-precision floating-point arithmetic.
    The Journal of Supercomputing 2013, Volume 64 (0) 2013
    Conference paper
    Yuanwu Lei, Yong Dou, Lei Guo, Jinbo Xu, Jie Zhou, Yazhuo Dong, Hongjian Li.
    VLIW coprocessor for IEEE-754 quadruple-precision elementary functions.
    TACO 2013, Volume 10 (0) 2013
    Conference paper
    Lei Guo, Yuhua Tang, Yong Dou, Yuanwu Lei, Meng Ma, Jie Zhou.
    Window Memory Layout Scheme for Alternate Row-Wise/Column-Wise Matrix Access.
    IEICE Transactions 2013, Volume 96 (0) 2013
    Conference paper
    Rongchun Li, Yong Dou, Yuanwu Lei, Shi-Ce Ni, Song Guo.
    Design and Implementation of the Parameterized Multi-Standard High-Throughput Radix-4 Viterbi Decoder on FPGA.
    IEICE Transactions 2012, Volume 95 (0) 2012
    Conference paper
    Yuanwu Lei, Yong Dou, Song Guo, Jie Zhou.
    FPGA Implementation of Variable-Precision Floating-Point Arithmetic.
    Advanced Parallel Processing Technologies - 9th International Symposium, APPT 2011, Shanghai, China, September 26-27, 2011. Proceedings 2011 (0) 2011
    Conference paper
    Yuanwu Lei, Yong Dou, Jie Zhou, Sufeng Wang.
    VPFPAP: A Special-Purpose VLIW Processor for Variable-Precision Floating-Point Arithmetic.
    International Conference on Field Programmable Logic and Applications, FPL 2011, September 5-7, Chania, Crete, Greece 2011 (0) 2011
    Conference paper
    Yuanwu Lei, Yong Dou, Jie Zhou.
    FPGA-Specific Custom VLIW Architecture for Arbitrary Precision Floating-Point Arithmetic.
    IEICE Transactions 2011, Volume 94 (0) 2011
    Conference paper
    Yuanwu Lei, Yong Dou, Li Shen 0001, Jie Zhou, Song Guo.
    Special-purposed VLIW architecture for IEEE-754 quadruple precision elementary functions on FPGA.
    IEEE 29th International Conference on Computer Design, ICCD 2011, Amherst, MA, USA, October 9-12, 2011 2011 (0) 2011
    Conference paper
    Yong Dou, Yuanwu Lei, Guiming Wu, Song Guo, Jie Zhou, Li Shen 0001.
    FPGA accelerating double/quad-double high precision floating-point applications for ExaScale computing.
    Proceedings of the 24th International Conference on Supercomputing, 2010, Tsukuba, Ibaraki, Japan, June 2-4, 2010 2010 (0) 2010
    Conference paper
    Yong Dou, Jie Zhou, Guiming Wu, Jingfei Jiang, Yuanwu Lei, Shi-Ce Ni.
    A Unified Co-Processor Architecture for Matrix Decomposition.
    J. Comput. Sci. Technol. 2009, Volume 25 (0) 2010
    Conference paper
    Yong Dou, Jie Zhou, Xiaoyang Chen, Yuanwu Lei, Jinbo Xu.
    FPGA accelerating three QR decomposition algorithms in the unified pipelined framework.
    19th International Conference on Field Programmable Logic and Applications, FPL 2009, August 31 - September 2, 2009, Prague, Czech Republic 2009 (0) 2009
    Conference paper
    Jie Zhou, Yong Dou, Jianxun Zhao, Fei Xia, Yuanwu Lei, Yuxing Tang.
    A Fine-Grained Pipelined Implementation for Large-Scale Matrix Inversion on FPGA.
    Advanced Parallel Processing Technologies, 8th International Symposium, APPT 2009, Rapperswil, Switzerland, August 24-25, 2009, Proceedings 2009 (0) 2009
    Conference paper
    Guiming Wu, Yong Dou, Yuanwu Lei, Jie Zhou, Miao Wang, Jingfei Jiang.
    A Fine-grained Pipelined Implementation of the LINPACK Benchmark on FPGAs.
    FCCM 2009, 17th IEEE Symposium on Field Programmable Custom Computing Machines, Napa, California, USA, 5-7 April 2009, Proceedings 2009 (0) 2009
    Conference paper
    Jie Zhou, Yazhuo Dong, Yong Dou, Yuanwu Lei.
    Dynamic Configurable Floating-Point FFT Pipelines and Hybrid-Mode CORDIC on FPGA.
    International Conference on Embedded Software and Systems, ICESS '09, Hangzhou, Zhejiang, P. R. China, May 25-27, 2009. 2009 (0) 2008
    Conference paper
    Baofeng Li, Yong Dou, Yuanwu Lei.
    Area and throughput trade-offs in design of arithmetic encoder for JPEG2000.
    IEEE Asia Pacific Conference on Circuits and Systems, APCCAS 2008, Macao, China, November 30 2008 - December 3, 2008 2008 (0) 2008
    Conference paper
    Jie Zhou, Yong Dou, Yuanwu Lei, Jinbo Xu, Yazhuo Dong.
    Double Precision Hybrid-Mode Floating-Point FPGA CORDIC Co-processor.
    10th IEEE International Conference on High Performance Computing and Communications, HPCC 2008, 25-27 Sept. 2008, Dalian, China 2008 (0) 2008
    Conference paper
    Jie Zhou, Yong Dou, Yuanwu Lei, Yazhuo Dong.
    Hybrid-Mode Floating-Point FPGA CORDIC Co-processor.
    Reconfigurable Computing: Architectures, Tools and Applications, 4th International Workshop, ARC 2008, London, UK, March 26-28, 2008. Proceedings 2008 (0) 2008
    Conference paper
    Yong Dou, Jie Zhou, Yuanwu Lei, Xingming Zhou.
    FPGA SAR Processor with Window Memory Accesses.
    IEEE International Conference on Application-Specific Systems, Architectures and Processors, ASAP 2007, Montréal, Québec, Canada, July 8-11, 2007 2007 (0) 2007
    Show item 1 to 29 of 29  

    Your query returned 29 matches in the database.