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First name:	Shen-Fu
Last name:	Hsiao
DBLP:	90/1566
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	Conference paper Shen-Fu Hsiao, Hou-Jen Ko, Yu-Ling Tseng, Wen-Liang Huang, Shin-Hung Lin, Chia-Sheng Wen. Design of Hardware Function Evaluators Using Low-Overhead Nonuniform Segmentation With Address Remapping.	IEEE Trans. VLSI Syst. 2013, Volume 21	(0)	2013
	Conference paper Shen-Fu Hsiao, Jun-Hong Zhang Jian, Ming-Chih Chen. Low-Cost FIR Filter Designs Based on Faithfully Rounded Truncated Multiple Constant Multiplication/Accumulation.	IEEE Trans. on Circuits and Systems 2013, Volume 60	(0)	2013
	Conference paper Shen-Fu Hsiao, Hou-Jen Ko, Chia-Sheng Wen. Two-Level Hardware Function Evaluation Based on Correction of Normalized Piecewise Difference Functions.	IEEE Trans. on Circuits and Systems 2012, Volume 59	(0)	2012
	Conference paper Shen-Fu Hsiao, Jin-Wen Cheng, Wen-Ling Wang, Guan-Fu Yeh. Low latency design of Depth-Image-Based Rendering using hybrid warping and hole-filling.	2012 IEEE International Symposium on Circuits and Systems, ISCAS 2012, Seoul, Korea (South), May 20-23, 2012 2012	(0)	2012
	Conference paper Shen-Fu Hsiao, Chia-Sheng Wen, Cheng-Han Lee, Andrew Lee. Low-cost designs of rectangular to polar coordinate converters for digital communication.	2012 IEEE Asia Pacific Conference on Circuits and Systems, APCCAS 2012, Kaohsiung, Taiwan, December 2-5, 2012 2012	(0)	2012
	Conference paper Shen-Fu Hsiao, Chi-Guang Lin, Po-Han Wu, Chia-Sheng Wen. Asynchronous AHB bus interface designs in a multiple-clock-domain graphics system.	2012 IEEE Asia Pacific Conference on Circuits and Systems, APCCAS 2012, Kaohsiung, Taiwan, December 2-5, 2012 2012	(0)	2012
	Journal article Hou-Jen Ko, Shen-Fu Hsiao. Design and Application of Faithfully Rounded and Truncated Multipliers With Combined Deletion, Reduction, Truncation, and Rounding.	IEEE Trans. on Circuits and Systems 2011, Volume 58	(0)	2011
	Conference paper Hou-Jen Ko, Shen-Fu Hsiao, Wen-Liang Huang. A new non-uniform segmentation and addressing remapping strategy for hardware-oriented function evaluators based on polynomial approximation.	International Symposium on Circuits and Systems (ISCAS 2010), May 30 - June 2, 2010, Paris, France 2010	(0)	2010
	Journal article Shen-Fu Hsiao, Ming-Yu Tsai, Chia-Sheng Wen. Low Area/Power Synthesis Using Hybrid Pass Transistor/CMOS Logic Cells in Standard Cell-Based Design Environment.	IEEE Trans. on Circuits and Systems 2010, Volume 57	(0)	2010
	Conference paper Ming-Chih Chen, Shen-Fu Hsiao. Low Cost Design of an Advanced Encryption Standard (AES) Processor Using a New Common-Subexpression-Elimination Algorithm.	IEICE Transactions 2009, Volume 92	(0)	2009
	Conference paper Liang-Bi Chen, Ruei-Ting Gu, Wei-Sheng Huang, Chien-Chou Wang, Wen-Chi Shiue, Tsung-Yu Ho, Yun-Nan Chang, Shen-Fu Hsiao, Chung-Nan Lee, Ing-Jer Huang. An 8.69 Mvertices/s 278 Mpixels/s tile-based 3D graphics SoC HW/SW development for consumer electronics.	Proceedings of the 14th Asia South Pacific Design Automation Conference, ASP-DAC 2009, Yokohama, Japan, January 19-22, 2009 2009	(0)	2009
	Conference paper Shen-Fu Hsiao, Ming-Yu Tsai, Chia-Sheng Wen. Area oriented pass-transistor logic synthesis using buffer elimination and layout compaction.	International Symposium on Circuits and Systems (ISCAS 2008), 18-21 May 2008, Sheraton Seattle Hotel, Seattle, Washington, USA 2008	(0)	2008
	Conference paper Shen-Fu Hsiao, Ping-Chung Wei, Ching-Pin Lin. An automatic hardware generator for special arithmetic functions using various ROM-based approximation approaches.	International Symposium on Circuits and Systems (ISCAS 2008), 18-21 May 2008, Sheraton Seattle Hotel, Seattle, Washington, USA 2008	(0)	2008
	Conference paper Shen-Fu Hsiao, Yo-Chi Chen, Ming-Yu Tsai, Tze-Chong Cheng. Novel Memory Organization and Circuit Designs for Efficient Data Access in Applications of 3D Graphics and Multimedia Coding.	14th IEEE International Workshop on Memory Technology, Design, and Testing (MTDT 2006), 2-4 August 2006, Taipei, Taiwan 2006	(0)	2006
	Conference paper Shen-Fu Hsiao, Sze-Yun Lin, Tze-Chong Cheng, Ming-Yu Tsai. An Automatic Cache Generator Based on Content-Addressable Memory.	IEEE Asia Pacific Conference on Circuits and Systems 2006, APCCAS 2006, Singapore, 4-7 December 2006 2006	(0)	2006
	Conference paper Shen-Fu Hsiao, Ming-Yu Tsai, Chia-Sheng Wen. Efficient Pass-Transistor-Logic Synthesis for Sequential Circuits.	IEEE Asia Pacific Conference on Circuits and Systems 2006, APCCAS 2006, Singapore, 4-7 December 2006 2006	(0)	2006
	Conference paper Shen-Fu Hsiao, Ming-Yu Tsai, Ming-Chih Chen, Chia-Sheng Wen. An efficient pass-transistor-logic synthesizer using multiplexers and inverters only.	International Symposium on Circuits and Systems (ISCAS 2005), 23-26 May 2005, Kobe, Japan 2005	(0)	2005
	Conference paper Tso-Bing Juang, Shen-Fu Hsiao, Ming-Yu Tsai, Jenq-Shiun Jan. A Cell-Driven Multiplier Generator with Delay Optimization of Partial Products Compression and an Efficient Partition Technique for the Final Addition.	IEICE Transactions 2005, Volume 88	(0)	2005
	Conference paper Ming-Chih Chen, Shen-Fu Hsiao, Cheng-Hsien Yang. Design and implementation of a video-oriented network-interface-card system.	Proceedings of the 2003 Asia and South Pacific Design Automation Conference, ASP-DAC '03, Kitakyushu, Japan, January 21-24, 2003 2003	(0)	2003
	Conference paper Tso-Bing Juang, Jeng-Hsiun Jan, Ming-Yu Tsai, Shen-Fu Hsiao. Partition methodology for the final adder in a tree-structure parallel multiplier generator.	IEEE Asia Pacific Conference on Circuits and Systems 2002, APCCAS 2002, Singapore, 16-18 December 2002 2002	(0)	2002
	Conference paper Shen-Fu Hsiao, Wei-Ren Shiue. A new hardware-efficient algorithm and architecture for computation of 2-D DCTs on a linear array.	IEEE Trans. Circuits Syst. Video Techn. 2001, Volume 11	(0)	2001
	Conference paper Shen-Fu Hsiao, Jian-Ming Tseng. Parallel, Pipelined and Folded Architectures for Computation of 1-D and 2-D DCT in Image and Video Codec.	VLSI Signal Processing 2001, Volume 28	(0)	2001
	Conference paper Shen-Fu Hsiao, Chun-Yi Lau, Jean-Marc Delosme. Redundant Constant-Factor Implementation of Multi-Dimensional CORDIC and Its Application to Complex SVD.	VLSI Signal Processing 2000, Volume 25	(0)	2000
	Conference paper Shen-Fu Hsiao. A high-speed constant-factor redundant CORDIC processor without extra correcting or scaling iterations.	International Symposium on Circuits and Systems (ISCAS 1999), May 30 - June 2, 1999, Orlando, Florida, USA 1999	(0)	1999
	Conference paper Shen-Fu Hsiao, Jen-Yin Chen. Design, Implementation and Analysis of a New Redundant CORDIC Processor with Constant Scaling Factor and Regular Structure.	VLSI Signal Processing 1998, Volume 20	(0)	1998

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