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    First name: Chittaranjan A.
    Last name: Mandal
    DBLP: m/ChittaranjanAMandal
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    Conference paper
    Kunal Banerjee, Dipankar Sarkar, Chittaranjan A. Mandal.
    Deriving bisimulation relations from path based equivalence checkers.
    Formal Asp. Comput. 2017, Volume 29 (0) 2017
    Journal article
    Jasaswi Prasad Mohanty, Chittaranjan A. Mandal, Chris Reade.
    Distributed construction of minimum Connected Dominating Set in wireless sensor network using two-hop information.
    Computer Networks 2017, Volume 123 (0) 2017
    Conference paper
    Soumyadip Bandyopadhyay, Santonu Sarkar, Dipankar Sarkar, Chittaranjan A. Mandal.
    SamaTulyata: An Efficient Path Based Equivalence Checking Tool.
    Automated Technology for Verification and Analysis - 15th International Symposium, ATVA 2017, Pune, India, October 3-6, 2017, Proceedings 2017 (0) 2017
    Conference paper
    Kunal Banerjee, Chittaranjan A. Mandal, Dipankar Sarkar.
    An Equivalence Checking Framework for Array-Intensive Programs.
    Automated Technology for Verification and Analysis - 15th International Symposium, ATVA 2017, Pune, India, October 3-6, 2017, Proceedings 2017 (0) 2017
    Conference paper
    Soumyadip Bandyopadhyay, Dipankar Sarkar, Chittaranjan A. Mandal.
    An efficient path based equivalence checking for Petri net based models of programs.
    Proceedings of the 9th India Software Engineering Conference, Goa, India, February 18-20, 2016 2016 (0) 2016
    Journal article
    Jasaswi Prasad Mohanty, Chittaranjan A. Mandal, Chris Reade, Ariyam Das.
    Construction of minimum connected dominating set in wireless sensor networks using pseudo dominating set.
    Ad Hoc Networks 2016, Volume 42 (0) 2016
    Conference paper
    Bapi Kar, Susmita Sur-Kolay, Chittaranjan A. Mandal.
    A Novel EPE Aware Hybrid Global Route Planner after Floorplanning.
    29th International Conference on VLSI Design and 15th International Conference on Embedded Systems, VLSID 2016, Kolkata, India, January 4-8, 2016 2016 (0) 2016
    Conference paper
    Kunal Banerjee, Chittaranjan A. Mandal, Dipankar Sarkar.
    Translation validation of loop and arithmetic transformations in the presence of recurrences.
    Proceedings of the 17th ACM SIGPLAN/SIGBED Conference on Languages, Compilers, Tools, and Theory for Embedded Systems, LCTES 2016, Santa Barbara, CA, USA, June 13 - 14, 2016 2016 (0) 2016
    Conference paper
    Soumyadip Bandyopadhyay, Dipankar Sarkar, Chittaranjan A. Mandal, Kunal Banerjee, Krishnam Raju Duddu.
    A Path Construction Algorithm for Translation Validation Using PRES+ Models.
    Parallel Processing Letters 2016, Volume 26 (0) 2016
    Conference paper
    Bapi Kar, Susmita Sur-Kolay, Chittaranjan A. Mandal.
    An early global routing framework for uniform wire distribution in SoCs.
    29th IEEE International System-on-Chip Conference, SOCC 2016, Seattle, WA, USA, September 6-9, 2016 2016 (0) 2016
    Conference paper
    Soumyadip Bandyopadhyay, Dipankar Sarkar, Kunal Banerjee, Chittaranjan A. Mandal.
    A Path-based Equivalence Checking Method for Petri Net based Models of Programs.
    ICSOFT-EA 2015 - Proceedings of the 10th International Conference on Software Engineering and Applications, Colmar, Alsace, France, 20-22 July, 2015. 2015 (0) 2015
    Conference paper
    Soumyadip Bandyopadhyay, Dipankar Sarkar, Chittaranjan A. Mandal.
    Poster: An Efficient Equivalence Checking Method for Petri Net Based Models of Programs.
    37th IEEE/ACM International Conference on Software Engineering, ICSE 2015, Florence, Italy, May 16-24, 2015, Volume 2 2015 (0) 2015
    Conference paper
    Kunal Banerjee, Chittaranjan A. Mandal, Dipankar Sarkar.
    Translation Validation of Transformations of Embedded System Specifications Using Equivalence Checking.
    2015 IEEE Computer Society Annual Symposium on VLSI, ISVLSI 2015, Montpellier, France, July 8-10, 2015 2015 (0) 2015
    Conference paper
    Soumyadip Bandyopadhyay, Dipankar Sarkar, Chittaranjan A. Mandal.
    Validating SPARK: High Level Synthesis Compiler.
    2015 IEEE Computer Society Annual Symposium on VLSI, ISVLSI 2015, Montpellier, France, July 8-10, 2015 2015 (0) 2015
    Conference paper
    Kunal Banerjee, Chittaranjan A. Mandal, Dipankar Sarkar.
    A translation validation framework for symbolic value propagation based equivalence checking of FSMDAs.
    15th IEEE International Working Conference on Source Code Analysis and Manipulation, SCAM 2015, Bremen, Germany, September 27-28, 2015 2015 (0) 2015
    Conference paper
    K. K. Sharma, Kunal Banerjee, Chittaranjan A. Mandal.
    Establishing Equivalence of Expressions: An Automated Evaluator Designer's Perspective.
    Mining Intelligence and Knowledge Exploration - Third International Conference, MIKE 2015, Hyderabad, India, December 9-11, 2015, Proceedings 2015 (0) 2015
    Conference paper
    K. K. Sharma, Kunal Banerjee, Chittaranjan A. Mandal.
    Determining Equivalence of Expressions: An Automated Evaluator's Perspective.
    Seventh IEEE International Conference on Technology for Education, T4E 2015, Warangal, India, December 10-12, 2015 2015 (0) 2015
    Conference paper
    Bapi Kar, Susmita Sur-Kolay, Chittaranjan A. Mandal.
    Global Routing Using Monotone Staircases with Minimal Bends.
    2014 27th International Conference on VLSI Design and 2014 13th International Conference on Embedded Systems, Mumbai, India, January 5-9, 2014 2014 (0) 2014
    Conference paper
    Kunal Banerjee, Chandan Karfa, Dipankar Sarkar, Chittaranjan A. Mandal.
    Verification of Code Motion Techniques Using Value Propagation.
    IEEE Trans. on CAD of Integrated Circuits and Systems 2014, Volume 33 (0) 2014
    Conference paper
    Partha De, Kunal Banerjee, Chittaranjan A. Mandal, Debdeep Mukhopadhyay.
    Circuits and Synthesis Mechanism for Hardware Design to Counter Power Analysis Attacks.
    17th Euromicro Conference on Digital System Design, DSD 2014, Verona, Italy, August 27-29, 2014 2014 (0) 2014
    Conference paper
    Kunal Banerjee, Dipankar Sarkar, Chittaranjan A. Mandal.
    Extending the FSMD Framework for Validating Code Motions of Array-Handling Programs.
    IEEE Trans. on CAD of Integrated Circuits and Systems 2014, Volume 33 (0) 2014
    Conference paper
    Kunal Banerjee, Chittaranjan A. Mandal, Dipankar Sarkar.
    Extending the scope of translation validation by augmenting path based equivalence checkers with SMT solvers.
    18th International Symposium on VLSI Design and Test, VDAT 2014, Coimbatore, India, July 16-18, 2014 2014 (0) 2014
    Conference paper
    Partha De, Kunal Banerjee, Chittaranjan A. Mandal.
    A BDD based secure hardware design method to guard against power analysis attacks.
    18th International Symposium on VLSI Design and Test, VDAT 2014, Coimbatore, India, July 16-18, 2014 2014 (0) 2014
    Conference paper
    Chandan Karfa, Dipankar Sarkar, Chittaranjan A. Mandal.
    Verification of KPN Level Transformations.
    26th International Conference on VLSI Design and 12th International Conference on Embedded Systems, Pune, India, January 5-10, 2013 2013 (0) 2013
    Conference paper
    Partha De, Kunal Banerjee, Chittaranjan A. Mandal, Debdeep Mukhopadhyay.
    Designing DPA Resistant Circuits Using BDD Architecture and Bottom Pre-charge Logic.
    2013 Euromicro Conference on Digital System Design, DSD 2013, Los Alamitos, CA, USA, September 4-6, 2013 2013 (0) 2013
    Conference paper
    Chandan Karfa, Kunal Banerjee, Dipankar Sarkar, Chittaranjan A. Mandal.
    Verification of Loop and Arithmetic Transformations of Array-Intensive Behaviors.
    IEEE Trans. on CAD of Integrated Circuits and Systems 2013, Volume 32 (0) 2013
    Conference paper
    Bapi Kar, Susmita Sur-Kolay, Chittaranjan A. Mandal.
    STAIRoute: Global routing using monotone staircase channels.
    IEEE Computer Society Annual Symposium on VLSI, ISVLSI 2013, Natal, Brazil, August 5-7, 2013 2013 (0) 2013
    Conference paper
    Ariyam Das, Chittaranjan A. Mandal, Chris Reade.
    Determining the User Intent Behind Web Search Queries by Learning from Past User Interactions with Search Results.
    19th International Conference on Management of Data, COMAD 2013, Ahmedabad, India, December 19-21, 2013 2013 (0) 2013
    Conference paper
    Arun Dobriyal, Rahul Gonnabattula, Pallab Dasgupta, Chittaranjan A. Mandal.
    Workload Driven Power Domain Partitioning.
    Progress in VLSI Design and Test - 16th International Symposium, VDAT 2012, Shibpur, India, July 1-4, 2012. Proceedings 2012 (0) 2012
    Conference paper
    Soumyadip Bandyopadhyay, Kunal Banerjee, Dipankar Sarkar, Chittaranjan A. Mandal.
    Translation Validation for PRES+ Models of Parallel Behaviours via an FSMD Equivalence Checker.
    Progress in VLSI Design and Test - 16th International Symposium, VDAT 2012, Shibpur, India, July 1-4, 2012. Proceedings 2012 (0) 2012
    Conference paper
    Bapi Kar, Susmita Sur-Kolay, Sridhar H. Rangarajan, Chittaranjan A. Mandal.
    A Faster Hierarchical Balanced Bipartitioner for VLSI Floorplans Using Monotone Staircase Cuts.
    Progress in VLSI Design and Test - 16th International Symposium, VDAT 2012, Shibpur, India, July 1-4, 2012. Proceedings 2012 (0) 2012
    Conference paper
    Chandan Karfa, Chittaranjan A. Mandal, Dipankar Sarkar.
    Formal verification of code motion techniques using data-flow-driven equivalence checking.
    ACM Trans. Design Autom. Electr. Syst. 2012, Volume 17 (0) 2012
    Conference paper
    Priyankar Ghosh, Aritra Hazra, Rahul Gonnabhaktula, Niraj Bhilegaonkar, Pallab Dasgupta, Chittaranjan A. Mandal, Krishna Paul.
    POWER-SIM: An SOC Simulator for Estimating Power Profiles of Mobile Workloads.
    J. Low Power Electronics 2012, Volume 8 (0) 2012
    Conference paper
    Chandan Karfa, Chittaranjan A. Mandal, Dipankar Sarkar.
    Verification of Register Transfer Level Low Power Transformations.
    IEEE Computer Society Annual Symposium on VLSI, ISVLSI 2011, 4-6 July 2011, Chennai, India 2011 (0) 2011
    Conference paper
    Chandan Karfa, K. Banerjee, Dipankar Sarkar, Chittaranjan A. Mandal.
    Equivalence Checking of Array-Intensive Programs.
    IEEE Computer Society Annual Symposium on VLSI, ISVLSI 2011, 4-6 July 2011, Chennai, India 2011 (0) 2011
    Conference paper
    Ariyam Das, Chittaranjan A. Mandal, Chris Reade, Manish Aasawat.
    An improved greedy construction of minimum connected dominating sets in wireless networks.
    2011 IEEE Wireless Communications and Networking Conference, WCNC 2011, Proceedings, Cancun, Mexico, 28-31 March, 2011 2011 (0) 2011
    Conference paper
    Soumya Pandit, Chittaranjan A. Mandal, Amit Patra.
    A Methodology for Generation of Performance Models for the Sizing of Analog High-Level Topologies.
    VLSI Design 2011, Volume 2011 (0) 2011
    Journal article
    S. Bandyopadhyay, Dipankar Sarkar, Chittaranjan A. Mandal.
    Equivalence Checking in Embedded Systems Design Verification
    CoRR 2010, Volume 0 (0) 2010
    Conference paper
    Soumya Pandit, Chittaranjan A. Mandal, Amit Patra.
    An automated high-level topology generation procedure for continuous-time SigmaDelta modulator.
    Integration 2010, Volume 43 (0) 2010
    Conference paper
    Debasish Karfa, Dipankar Sarkar, Chittaranjan A. Mandal.
    Verification of Datapath and Controller Generation Phase in High-Level Synthesis of Digital Circuits.
    IEEE Trans. on CAD of Integrated Circuits and Systems 2010, Volume 29 (0) 2010
    Conference paper
    Chandan Karfa, Dipankar Sarkar, Chittaranjan A. Mandal.
    Data-Flow Driven Equivalence Checking for Verification of Code Motion Techniques.
    (0) 2010
    Conference paper
    Gopal Paul, Santosh Biswas, Chittaranjan A. Mandal, Bhargab B. Bhattacharya.
    A BDD-based approach to design power-aware on-line detectors for digital circuits.
    Annual IEEE International SoC Conference, SoCC 2010, September 27-29, 2010, Las Vegas, NV, USA, Proceedings 2010 (0) 2010
    Conference paper
    Rajiv Misra, Chittaranjan A. Mandal.
    Minimum Connected Dominating Set Using a Collaborative Cover Heuristic for Ad Hoc Sensor Networks.
    IEEE Trans. Parallel Distrib. Syst. 2010, Volume 21 (0) 2010
    Conference paper
    Rajiv Misra, Chittaranjan A. Mandal.
    Location Updates of Mobile Node in Wireless Sensor Networks.
    MSN 2009, The Fifth International Conference on Mobile Ad-hoc and Sensor Networks, Wu Yi Mountain, Fujian, China , December 14-16, 2009 2009 (0) 2009
    Conference paper
    Soumya Pandit, Chittaranjan A. Mandal, Amit Patra.
    Systematic Methodology for High-Level Performance Modeling of Analog Systems.
    VLSI Design 2009: Improving Productivity through Higher Abstraction, The 22nd International Conference on VLSI Design, New Delhi, India, 5-9 January 2009 2009 (0) 2009
    Conference paper
    Rajiv Misra, Chittaranjan A. Mandal.
    Rotation of CDS via Connected Domatic Partition in Ad Hoc Sensor Networks.
    IEEE Trans. Mob. Comput. 2009, Volume 8 (0) 2009
    Conference paper
    Rajiv Misra, Chittaranjan A. Mandal.
    Efficient clusterhead rotation
    Wireless Communications and Mobile Computing 2009, Volume 9 (0) 2009
    Conference paper
    Chandan Karfa, Dipankar Sarkar, Chittaranjan A. Mandal, P. Kumar.
    An Equivalence-Checking Method for Scheduling Verification in High-Level Synthesis.
    IEEE Trans. on CAD of Integrated Circuits and Systems 2008, Volume 27 (0) 2008
    Conference paper
    Soumya Pandit, Sumit K. Bhattacharya, Chittaranjan A. Mandal, Amit Patra.
    A Fast Exploration Procedure for Analog High-Level Specification Translation.
    IEEE Trans. on CAD of Integrated Circuits and Systems 2008, Volume 27 (0) 2008
    Journal article
    Amit Kumar Mandal, Chittaranjan A. Mandal, Chris Reade.
    A System for Automatic Evaluation of C Programs: Features and Interfaces.
    IJWLTT 2007, Volume 2 (0) 2007
    Conference paper
    Chittaranjan A. Mandal, Chris Reade.
    Recipient Specific Electronic Cash - A Scheme for Recipient Specific Yet Anonymous and Tranferable Electronic Cash.
    WEBIST 2007 - Proceedings of the Third International Conference on Web Information Systems and Technologies, Volume SeBeG/eL, Barcelona, Spain, March 3-6, 2007. 2007 (0) 2007
    Conference paper
    Rajiv Misra, Chittaranjan A. Mandal.
    ClusterHead Rotation via Domatic Partition in Self-Organizing Sensor Networks.
    Proceedings of the Second International Conference on COMmunication System softWAre and MiddlewaRE (COMSWARE 2007), January 7-12, 2007, Bangalore, India 2007 (0) 2007
    Conference paper
    Chandan Karfa, Dipankar Sarkar, Chittaranjan A. Mandal, Chris Reade.
    Hand-in-hand verification of high-level synthesis.
    Proceedings of the 17th ACM Great Lakes Symposium on VLSI 2007, Stresa, Lago Maggiore, Italy, March 11-13, 2007 2007 (0) 2007
    Conference paper
    Vinay Vishwakarma, Chittaranjan A. Mandal, Shamik Sural.
    Automatic Detection of Human Fall in Video.
    Pattern Recognition and Machine Intelligence, Second International Conference, PReMI 2007, Kolkata, India, December 18-22, 2007, Proceedings 2007 (0) 2007
    Conference paper
    Chandan Karfa, Chittaranjan A. Mandal, Dipankar Sarkar, Chris Reade.
    Register Sharing Verification During Data-Path Synthesis.
    2007 International Conference on Computing: Theory and Applications (ICCTA 2007), 5-7 March 2007, Kolkata, India 2007 (0) 2007
    Conference paper
    Soumya Pandit, Sougata Kar, Chittaranjan A. Mandal, Amit Patra.
    High level synthesis of higher order continuous time state variable filters with minimum sensitivity and hardware count.
    Proceedings of the Conference on Design, Automation and Test in Europe, DATE 2006, Munich, Germany, March 6-10, 2006 2006 (0) 2006
    Conference paper
    Soumya Pandit, Chittaranjan A. Mandal, Amit Patra.
    A formal approach for high level synthesis of linear analog systems.
    Proceedings of the 16th ACM Great Lakes Symposium on VLSI 2006, Philadelphia, PA, USA, April 30 - May 1, 2006 2006 (0) 2006
    Conference paper
    Chandan Karfa, Chittaranjan A. Mandal, Dipankar Sarkar, S. R. Pentakota, Chris Reade.
    A Formal Verification Method of Scheduling in High-level Synthesis.
    7th International Symposium on Quality of Electronic Design (ISQED 2006), 27-29 March 2006, San Jose, CA, USA 2006 (0) 2006
    Conference paper
    Chandan Karfa, Chittaranjan A. Mandal, Dipankar Sarkar, S. R. Pentakota, Chris Reade.
    Verification of Scheduling in High-level Synthesis.
    2006 IEEE Computer Society Annual Symposium on VLSI (ISVLSI 2006), 2-3 March 2006, Karlsruhe, Germany 2006 (0) 2006
    Conference paper
    Amit Kumar Mandal, Chittaranjan A. Mandal, Chris Reade.
    A System for Automatic Evaluation of Programs for Correctness and Performance.
    WEBIST 2006, Proceedings of the Second International Conference on Web Information Systems and Technologies: Society, e-Business and e-Government / e-Learning, Setúbal, Portugal, April 11-13, 2006 2006 (0) 2006
    Conference paper
    Chittaranjan A. Mandal, Chris Reade.
    Animating Algorithms over the Web.
    WEBIST 2006, Proceedings of the Second International Conference on Web Information Systems and Technologies: Society, e-Business and e-Government / e-Learning, Setúbal, Portugal, April 11-13, 2006 2006 (0) 2006
    Conference paper
    Amit Kumar Mandal, Chittaranjan A. Mandal, Chris Reade.
    A System for Automatic Evaluation of Programs for Correctness and Performance.
    Web Information Systems and Technologies, International Conferences, WEBIST 2005 and WEBIST 2006. Revised Selected Papers 2007 (0) 2006
    Conference paper
    Arijit Mondal, P. P. Chakrabarti, Chittaranjan A. Mandal.
    A New Approach to Timing Analysis Using Event Propagation and Temporal Logic.
    2004 Design, Automation and Test in Europe Conference and Exposition (DATE 2004), 16-20 February 2004, Paris, France 2004 (0) 2004
    Conference paper
    B. Rajendran, V. Kheterpal, A. Das, J. Majumder, Chittaranjan A. Mandal, P. P. Chakrabarti.
    Timing analysis of tree-like RLC circuits.
    ISCAS (4) 2002 (0) 2002
    Conference paper
    Chittaranjan A. Mandal, R. M. Zimmer.
    A Genetic Algorithm for the Synthesis of Structured Data Paths.
    13th International Conference on VLSI Design (VLSI Design 2000), 4-7 January 2000, Calcutta, India 2000 (0) 2000
    Conference paper
    Chittaranjan A. Mandal, P. P. Chakrabarti, Sujoy Ghose.
    GABIND: a GA approach to allocation and binding for the high-level synthesis of data paths.
    IEEE Trans. VLSI Syst. 2000, Volume 8 (0) 2000
    Conference paper
    Chittaranjan A. Mandal, P. P. Chakrabarti, Sujoy Ghose.
    A design space exploration scheme for data-path synthesis.
    IEEE Trans. VLSI Syst. 1999, Volume 7 (0) 1999
    Conference paper
    Chittaranjan A. Mandal, P. P. Chakrabarti, Sujoy Ghose.
    Design Space Exploration for Data Path Synthesis.
    10th International Conference on VLSI Design (VLSI Design 1997), 4-7 January 1997, Hyderabad, India 1997 (0) 1997
    Conference paper
    Chittaranjan A. Mandal, P. P. Chakrabarti, Sujoy Ghose.
    Allocation and Binding in Data Path Synthesis Using a Genetic Algorithm Approach.
    9th International Conference on VLSI Design (VLSI Design 1996), 3-6 January 1996, Bangalore, India 1996 (0) 1996
    Conference paper
    Chittaranjan A. Mandal, P. P. Chakrabarti, Sujoy Ghose.
    Interconnect Optimization Techniques in Data Path Synthesis.
    Proceedings of the Fifth International Conference on VLSI Design, VLSI Design 1992, Bangalore, India, January 4-7, 1992 1992 (0) 1992
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