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A high parallel macro block level layered LDPC decoding architecture based on dedicated matrix reordering.

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    Title: A high parallel macro block level layered LDPC decoding architecture based on dedicated matrix reordering.
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    Date: 2011
    Publication type: Conference paper
    Authors:
    No. First name Last name Show
    1. Qian Xie
    2. Qian He
    3. Xiao Peng
    4. Ying Cui
    5. Zhixiang Chen
    6. Dajiang Zhou
    7. Satoshi Goto
    Download (by DOI): 10.1109/SiPS.2011.6088961
    BibTeX: conf/sips/XieHPCCZG11
    DBLP: db/conf/sips/sips2011.html#XieHPCCZG11
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    Conference
    Name: Proceedings of the IEEE Workshop on Signal Processing Systems, SiPS 2011, October 4-7, 2011, Beirut, Lebanon 2011
    URL: http://ieeexplore.ieee.org/xpl/mostRecentIssue.jsp?punumber=6086638
    DBLP: db/conf/sips/sips2011.html