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The Physical Design of Very Large Scale
Integrated Circuits (VLSIs) raised a lot of challenges,
because of the increasing designs complexity, the shrinking
of technological nodes and the decreasing of the allocated
power budget. This makes the traditional place and route
(P&R) flows unable to meet timing & power requirements.
To resolve such critical challenges, new P&R algorithms and
flows need to be developed to get the best possible results.