Publications
Search

Publications :: Search

A Max Capacitance Constraining Approach for Power Reduction in Advanced Nodes

Show publication

On this page you see the details of the selected publication.

    Publication properties
    Title: A Max Capacitance Constraining Approach for Power Reduction in Advanced Nodes
    Rating: (not rated yet)
    Discussion: 0 comments
    Date: 2018
    Publication type: Seminar work
    Authors:
    No. First name Last name Show
    1. IPCO CONF
    Bookmark:

    The following keywords have been assigned to this publication so far. If you have logged in, you can tag this publication with additional keywords.

    Keywords
    No keywords have been assigned to this publication yet.

    If you log in you can tag this publication with additional keywords

    A publication can refer to another publication (outgoing references) or it can be referred to by other publications (incoming references).

    Incoming References
    No incoming references have been assigned to this publication yet.
    Outgoing References
    No outgoing references have been assigned to this publication yet.

    If you log in you can add references to other publications

    A publication can be assigned to a conference, a journal or a school.

    Venue
    ICD Division- Rabat, Morocco

    Abstract

    The Physical Design of Very Large Scale Integrated Circuits (VLSIs) raised a lot of challenges, because of the increasing designs’ complexity, the shrinking of technological nodes and the decreasing of the allocated power budget. This makes the traditional place and route (P&R) flows unable to meet timing & power requirements. To resolve such critical challenges, new P&R algorithms and flows need to be developed to get the best possible results.