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Conference
Name:	15th IEEE International Symposium on Defect and Fault-Tolerance in VLSI Systems (DFT 2000), 25-27 October 2000, Yamanashi, Japan, Proceedings 2000
DBLP:	db/conf/dft/dft2000.html
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	Conference paper Monica Alderighi, Sergio D'Angelo, Giacomo R. Sechi, Cecilia Metra. Achieving Fault-Tolerance by Shifted and Rotated Operands in TMR Non-Diverse ALUs.	15th IEEE International Symposium on Defect and Fault-Tolerance in VLSI Systems (DFT 2000), 25-27 October 2000, Yamanashi, Japan, Proceedings 2000	(0)	2000
	Conference paper Gian-Carlo Cardarilli, Adelio Salsano, P. Marinucci, Marco Ottavi. A Fault-Tolerant 176 Gbit Solid State Mass Memory Architecture.	15th IEEE International Symposium on Defect and Fault-Tolerance in VLSI Systems (DFT 2000), 25-27 October 2000, Yamanashi, Japan, Proceedings 2000	(0)	2000
	Conference paper Lörinc Antoni, Régis Leveugle, Béla Fehér. Using Run-Time Reconfiguration for Fault Injection in Hardware Prototypes.	15th IEEE International Symposium on Defect and Fault-Tolerance in VLSI Systems (DFT 2000), 25-27 October 2000, Yamanashi, Japan, Proceedings 2000	(0)	2000
	Conference paper Andrea Baldini, Alfredo Benso, Silvia Chiusano, Paolo Prinetto. 'BOND': An Interposition Agents Based Fault Injector for Windows NT.	15th IEEE International Symposium on Defect and Fault-Tolerance in VLSI Systems (DFT 2000), 25-27 October 2000, Yamanashi, Japan, Proceedings 2000	(0)	2000
	Conference paper Juan Carlos Baraza, Joaquin Gracia, Daniel Gil, Pedro J. Gil. A Prototype of a VHDL-Based Fault Injection Tool.	15th IEEE International Symposium on Defect and Fault-Tolerance in VLSI Systems (DFT 2000), 25-27 October 2000, Yamanashi, Japan, Proceedings 2000	(0)	2000
	Conference paper Alfredo Benso, Silvia Chiusano, Paolo Prinetto, P. Simonotti, G. Ugo. Self-Repairing in a Micro-Programmed Processor for Dependable Applications.	15th IEEE International Symposium on Defect and Fault-Tolerance in VLSI Systems (DFT 2000), 25-27 October 2000, Yamanashi, Japan, Proceedings 2000	(0)	2000
	Conference paper Chuang Cheng, Chih-Tsun Huang, Jing-Reng Huang, Cheng-Wen Wu, Chen-Jong Wey, Ming-Chang Tsai. BRAINS: A BIST Compiler for Embedded Memories.	15th IEEE International Symposium on Defect and Fault-Tolerance in VLSI Systems (DFT 2000), 25-27 October 2000, Yamanashi, Japan, Proceedings 2000	(0)	2000
	Conference paper Ching-Hwa Cheng, Jinn-Shyan Wang, Shih-Chieh Chang, Wen-Ben Jone. Low-Speed Scan Testing of Charge-Sharing Faults for CMOS Domino Circuits.	15th IEEE International Symposium on Defect and Fault-Tolerance in VLSI Systems (DFT 2000), 25-27 October 2000, Yamanashi, Japan, Proceedings 2000	(0)	2000
	Conference paper Giuseppe Biasoli, Fabrizio Ferrandi, Donatella Sciuto, Alessandro Fin, Franco Fummi. BIST Architectures Selection Based on Behavioral Testing.	15th IEEE International Symposium on Defect and Fault-Tolerance in VLSI Systems (DFT 2000), 25-27 October 2000, Yamanashi, Japan, Proceedings 2000	(0)	2000
	Conference paper Serge N. Demidenko, Eugene M. Levine, Vincenzo Piuri. Synthesis of On-Line Testing Control Units: Flow Graph Coding/Monitoring Approach.	15th IEEE International Symposium on Defect and Fault-Tolerance in VLSI Systems (DFT 2000), 25-27 October 2000, Yamanashi, Japan, Proceedings 2000	(0)	2000

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