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    Conference
    Name: 2017 IEEE International Symposium on High Performance Computer Architecture, HPCA 2017, Austin, TX, USA, February 4-8, 2017 2017
    URL: http://ieeexplore.ieee.org/xpl/mostRecentIssue.jsp?punumber=7920262
    DBLP: db/conf/hpca/hpca2017.html
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    Below you find the publications assigned to this venue.

    Show item 1 to 10 of 55  
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    Conference paper
    Qiuyun Llull, Songchun Fan, Seyed Majid Zahedi, Benjamin C. Lee.
    Cooper: Task Colocation with Cooperative Games.
    2017 IEEE International Symposium on High Performance Computer Architecture, HPCA 2017, Austin, TX, USA, February 4-8, 2017 2017 (0) 2017
    Conference paper
    Derek Hower, Harold W. Cain, Carl A. Waldspurger.
    PABST: Proportionally Allocated Bandwidth at the Source and Target.
    2017 IEEE International Symposium on High Performance Computer Architecture, HPCA 2017, Austin, TX, USA, February 4-8, 2017 2017 (0) 2017
    Conference paper
    Jayesh Gaur, Mainak Chaudhuri, Pradeep Ramachandran, Sreenivas Subramoney.
    Near-Optimal Access Partitioning for Memory Hierarchies with Multiple Heterogeneous Bandwidth Sources.
    2017 IEEE International Symposium on High Performance Computer Architecture, HPCA 2017, Austin, TX, USA, February 4-8, 2017 2017 (0) 2017
    Conference paper
    Karthik Swaminathan, Nandhini Chandramoorthy, Chen-Yong Cher, Ramon Bertran Monfort, Alper Buyuktosunoglu, Pradip Bose.
    BRAVO: Balanced Reliability-Aware Voltage Optimization.
    2017 IEEE International Symposium on High Performance Computer Architecture, HPCA 2017, Austin, TX, USA, February 4-8, 2017 2017 (0) 2017
    Conference paper
    Rajiv Nishtala, Paul M. Carpenter, Vinicius Petrucci, Xavier Martorell.
    Hipster: Hybrid Task Manager for Latency-Critical Cloud Workloads.
    2017 IEEE International Symposium on High Performance Computer Architecture, HPCA 2017, Austin, TX, USA, February 4-8, 2017 2017 (0) 2017
    Conference paper
    Yao Wang, Benjamin Wu, G. Edward Suh.
    Secure Dynamic Memory Scheduling Against Timing Channel Attacks.
    2017 IEEE International Symposium on High Performance Computer Architecture, HPCA 2017, Austin, TX, USA, February 4-8, 2017 2017 (0) 2017
    Conference paper
    Sebastian Werner, Javier Navaridas, Mikel Luján.
    Designing Low-Power, Low-Latency Networks-on-Chip by Optimally Combining Electrical and Optical Links.
    2017 IEEE International Symposium on High Performance Computer Architecture, HPCA 2017, Austin, TX, USA, February 4-8, 2017 2017 (0) 2017
    Conference paper
    Thiruvengadam Vijayaraghavan, Yasuko Eckert, Gabriel H. Loh, Michael J. Schulte, Mike Ignatowski, Bradford M. Beckmann, William C. Brantley, Joseph L. Greathouse, Wei Huang, Arun Karunanithi, Onur Kayiran, Mitesh R. Meswani, Indrani Paul, Matthew Poremba, Steven E. Raasch, Steven K. Reinhardt, Greg Sadowski, Vilas Sridharan.
    Design and Analysis of an APU for Exascale Computing.
    2017 IEEE International Symposium on High Performance Computer Architecture, HPCA 2017, Austin, TX, USA, February 4-8, 2017 2017 (0) 2017
    Conference paper
    Rakesh Kumar 0003, Cheng-Chieh Huang, Boris Grot, Vijay Nagarajan.
    Boomerang: A Metadata-Free Architecture for Control Flow Delivery.
    2017 IEEE International Symposium on High Performance Computer Architecture, HPCA 2017, Austin, TX, USA, February 4-8, 2017 2017 (0) 2017
    Conference paper
    Yebin Lee, Hyeonggyu Kim, Seokin Hong, Soontae Kim.
    Partial Row Activation for Low-Power DRAM System.
    2017 IEEE International Symposium on High Performance Computer Architecture, HPCA 2017, Austin, TX, USA, February 4-8, 2017 2017 (0) 2017
    Show item 1 to 10 of 55  

    Your query returned 55 matches in the database.